[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h
Chris Lattner
lattner at cs.uiuc.edu
Sun Mar 5 13:08:18 PST 2006
Changes in directory llvm/include/llvm/CodeGen:
ScheduleDAG.h updated: 1.10 -> 1.11
---
Log message:
Add a new scheduling type. This is, of course, a hack. Proper factoring
will come later.
---
Diffs of the changes: (+8 -3)
ScheduleDAG.h | 11 ++++++++---
1 files changed, 8 insertions(+), 3 deletions(-)
Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.10 llvm/include/llvm/CodeGen/ScheduleDAG.h:1.11
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.10 Fri Feb 24 12:53:51 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h Sun Mar 5 15:08:06 2006
@@ -34,17 +34,16 @@
typedef std::vector<NodeInfoPtr> NIVector;
typedef std::vector<NodeInfoPtr>::iterator NIIterator;
-
// Scheduling heuristics
enum SchedHeuristics {
defaultScheduling, // Let the target specify its preference.
noScheduling, // No scheduling, emit breath first sequence.
simpleScheduling, // Two pass, min. critical path, max. utilization.
simpleNoItinScheduling, // Same as above exact using generic latency.
- listSchedulingBURR // Bottom up reg reduction list scheduling.
+ listSchedulingBURR, // Bottom up reg reduction list scheduling.
+ listSchedulingG5 // G5-specific scheduler. FIXME: parameterize better
};
-
//===--------------------------------------------------------------------===//
///
/// Node group - This struct is used to manage flagged node groups.
@@ -359,6 +358,12 @@
/// reduction list scheduler.
ScheduleDAG* createBURRListDAGScheduler(SelectionDAG &DAG,
MachineBasicBlock *BB);
+
+ /// createTDG5ListDAGScheduler - This creates a top-down list scheduler for
+ /// the PowerPC G5. FIXME: pull the priority function out into the PPC
+ /// backend!
+ ScheduleDAG* createTDG5ListDAGScheduler(SelectionDAG &DAG,
+ MachineBasicBlock *BB);
}
#endif
More information about the llvm-commits
mailing list