[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.98 -> 1.99
X86InstrInfo.td updated: 1.250 -> 1.251
---
Log message:

remove the read/write port/io intrinsics.


---
Diffs of the changes:  (+12 -21)

 X86ISelLowering.cpp |    9 ---------
 X86InstrInfo.td     |   24 ++++++++++++------------
 2 files changed, 12 insertions(+), 21 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.98 llvm/lib/Target/X86/X86ISelLowering.cpp:1.99
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.98	Tue Feb 28 19:11:20 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Thu Mar  2 18:19:44 2006
@@ -137,15 +137,6 @@
   setOperationAction(ISD::READCYCLECOUNTER , MVT::i64  , Custom);
   setOperationAction(ISD::BSWAP            , MVT::i16  , Expand);
 
-  setOperationAction(ISD::READIO           , MVT::i1   , Expand);
-  setOperationAction(ISD::READIO           , MVT::i8   , Expand);
-  setOperationAction(ISD::READIO           , MVT::i16  , Expand);
-  setOperationAction(ISD::READIO           , MVT::i32  , Expand);
-  setOperationAction(ISD::WRITEIO          , MVT::i1   , Expand);
-  setOperationAction(ISD::WRITEIO          , MVT::i8   , Expand);
-  setOperationAction(ISD::WRITEIO          , MVT::i16  , Expand);
-  setOperationAction(ISD::WRITEIO          , MVT::i32  , Expand);
-
   // These should be promoted to a larger select which is supported.
   setOperationAction(ISD::SELECT           , MVT::i1   , Promote);
   setOperationAction(ISD::SELECT           , MVT::i8   , Promote);


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.250 llvm/lib/Target/X86/X86InstrInfo.td:1.251
--- llvm/lib/Target/X86/X86InstrInfo.td:1.250	Sat Feb 25 04:02:21 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td	Thu Mar  2 18:19:44 2006
@@ -581,48 +581,48 @@
 //
 def IN8rr  : I<0xEC, RawFrm, (ops),
                "in{b} {%dx, %al|%AL, %DX}",
-               [(set AL, (readport DX))]>,  Imp<[DX], [AL]>;
+               []>,  Imp<[DX], [AL]>;
 def IN16rr : I<0xED, RawFrm, (ops),
                "in{w} {%dx, %ax|%AX, %DX}",
-               [(set AX, (readport DX))]>,  Imp<[DX], [AX]>, OpSize;
+               []>,  Imp<[DX], [AX]>, OpSize;
 def IN32rr : I<0xED, RawFrm, (ops),
                "in{l} {%dx, %eax|%EAX, %DX}",
-               [(set EAX, (readport DX))]>, Imp<[DX],[EAX]>;
+               []>, Imp<[DX],[EAX]>;
 
 def IN8ri  : Ii8<0xE4, RawFrm, (ops i16i8imm:$port),
                   "in{b} {$port, %al|%AL, $port}",
-                 [(set AL, (readport i16immZExt8:$port))]>,
+                 []>,
              Imp<[], [AL]>;
 def IN16ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
                   "in{w} {$port, %ax|%AX, $port}",
-                 [(set AX, (readport i16immZExt8:$port))]>,
+                 []>,
              Imp<[], [AX]>, OpSize;
 def IN32ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
                   "in{l} {$port, %eax|%EAX, $port}",
-                 [(set EAX, (readport i16immZExt8:$port))]>,
+                 []>,
              Imp<[],[EAX]>;
 
 def OUT8rr  : I<0xEE, RawFrm, (ops),
                 "out{b} {%al, %dx|%DX, %AL}",
-                [(writeport AL, DX)]>,  Imp<[DX,  AL], []>;
+                []>,  Imp<[DX,  AL], []>;
 def OUT16rr : I<0xEF, RawFrm, (ops),
                 "out{w} {%ax, %dx|%DX, %AX}",
-                [(writeport AX, DX)]>,  Imp<[DX,  AX], []>, OpSize;
+                []>,  Imp<[DX,  AX], []>, OpSize;
 def OUT32rr : I<0xEF, RawFrm, (ops),
                 "out{l} {%eax, %dx|%DX, %EAX}",
-                [(writeport EAX, DX)]>, Imp<[DX, EAX], []>;
+                []>, Imp<[DX, EAX], []>;
 
 def OUT8ir  : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
                    "out{b} {%al, $port|$port, %AL}",
-                   [(writeport AL, i16immZExt8:$port)]>,
+                   []>,
               Imp<[AL], []>;
 def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
                    "out{w} {%ax, $port|$port, %AX}",
-                   [(writeport AX, i16immZExt8:$port)]>,
+                   []>,
               Imp<[AX], []>, OpSize;
 def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
                    "out{l} {%eax, $port|$port, %EAX}",
-                   [(writeport EAX, i16immZExt8:$port)]>,
+                   []>,
               Imp<[EAX], []>;
 
 //===----------------------------------------------------------------------===//