[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Chris Lattner
lattner at cs.uiuc.edu
Mon Feb 27 22:49:50 PST 2006
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.112 -> 1.113
---
Log message:
Compile:
unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }
to:
_foo4:
lbz r3,1(r3)
blr
_foo5:
lbz r3,1(r3)
blr
not:
_foo4:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
_foo5:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
---
Diffs of the changes: (+17 -10)
DAGCombiner.cpp | 27 +++++++++++++++++----------
1 files changed, 17 insertions(+), 10 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.112 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.113
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.112 Tue Feb 28 00:35:35 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Feb 28 00:49:37 2006
@@ -1043,9 +1043,13 @@
}
}
- // fold (and (load x), 255) -> (zextload x)
- if (N1C && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
- MVT::ValueType EVT;
+ // fold (and (load x), 255) -> (zextload x, i8)
+ // fold (and (extload x, i16), 255) -> (zextload x, i8)
+ if (N1C &&
+ (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD ||
+ N0.getOpcode() == ISD::ZEXTLOAD) &&
+ N0.hasOneUse()) {
+ MVT::ValueType EVT, LoadedVT;
if (N1C->getValue() == 255)
EVT = MVT::i8;
else if (N1C->getValue() == 65535)
@@ -1054,17 +1058,20 @@
EVT = MVT::i32;
else
EVT = MVT::Other;
- if (EVT != MVT::Other) {
- assert(MVT::getSizeInBits(VT) > MVT::getSizeInBits(EVT) &&
- "Cannot zext to larger type!");
+
+ LoadedVT = N0.getOpcode() == ISD::LOAD ? VT :
+ cast<VTSDNode>(N0.getOperand(3))->getVT();
+ if (EVT != MVT::Other && LoadedVT > EVT) {
MVT::ValueType PtrType = N0.getOperand(1).getValueType();
// For big endian targets, we need to add an offset to the pointer to load
// the correct bytes. For little endian systems, we merely need to read
// fewer bytes from the same pointer.
- uint64_t PtrOff = (MVT::getSizeInBits(VT) - MVT::getSizeInBits(EVT)) / 8;
- SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
- DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
- DAG.getConstant(PtrOff, PtrType));
+ unsigned PtrOff =
+ (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
+ SDOperand NewPtr = N0.getOperand(1);
+ if (!TLI.isLittleEndian())
+ NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
+ DAG.getConstant(PtrOff, PtrType));
WorkList.push_back(NewPtr.Val);
SDOperand Load =
DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr,
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