[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGISel.h

[Chris Lattner]

Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGISel.h updated: 1.8 -> 1.9
---
Log message:

Add some hooks for selecting memory addresses.


---
Diffs of the changes:  (+17 -0)

 SelectionDAGISel.h |   17 +++++++++++++++++
 1 files changed, 17 insertions(+)


Index: llvm/include/llvm/CodeGen/SelectionDAGISel.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.8 llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.9
--- llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.8	Fri Jan 20 20:32:06 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGISel.h	Thu Feb 23 20:12:52 2006
@@ -49,11 +49,28 @@
   virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
   virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
 
+  /// SelectInlineAsmMemoryOperand - Select the specified address as a target
+  /// addressing mode, according to the specified constraint code.  If this does
+  /// not match or is not implemented, return true.  The resultant operands
+  /// (which will appear in the machine instruction) should be added to the
+  /// OutOps vector.
+  virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+                                            char ConstraintCode,
+                                            std::vector<SDOperand> &OutOps,
+                                            SelectionDAG &DAG) {
+    return true;
+  }
+  
 protected:
   /// Pick a safe ordering and emit instructions for each target node in the
   /// graph.
   void ScheduleAndEmitDAG(SelectionDAG &DAG);
   
+  /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
+  /// by tblgen.  Others should not call it.
+  void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
+                                     SelectionDAG &DAG);
+  
 private:
   SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
                                        Value *V, unsigned Reg);