[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Nate Begeman]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.95 -> 1.96
---
Log message:

handle combining A / (B << N) into A >>u (log2(B)+N) when B is a power of 2


---
Diffs of the changes:  (+13 -2)

 DAGCombiner.cpp |   15 +++++++++++++--
 1 files changed, 13 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.95 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.96
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.95	Fri Feb  3 16:24:05 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Sun Feb  5 01:20:23 2006
@@ -778,15 +778,26 @@
     return DAG.getNode(ISD::UDIV, VT, N0, N1);
   // fold (udiv x, (1 << c)) -> x >>u c
   if (N1C && isPowerOf2_64(N1C->getValue()))
-    return DAG.getNode(ISD::SRL, N->getValueType(0), N0,
+    return DAG.getNode(ISD::SRL, VT, N0, 
                        DAG.getConstant(Log2_64(N1C->getValue()),
                                        TLI.getShiftAmountTy()));
+  // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
+  if (N1.getOpcode() == ISD::SHL) {
+    if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
+      if (isPowerOf2_64(SHC->getValue())) {
+        MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
+        return DAG.getNode(ISD::SRL, VT, N0, 
+                           DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
+                                       DAG.getConstant(Log2_64(SHC->getValue()),
+                                                       ADDVT)));
+      }
+    }
+  }
   // fold (udiv x, c) -> alternate
   if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
     SDOperand Op = BuildUDIV(N);
     if (Op.Val) return Op;
   }
-      
   return SDOperand();
 }