[llvm-commits] CVS: llvm/lib/Target/X86/X86.td X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td X86Subtarget.h
Chris Lattner
lattner at cs.uiuc.edu
Tue Jan 31 11:43:47 PST 2006
Changes in directory llvm/lib/Target/X86:
X86.td updated: 1.20 -> 1.21
X86ISelLowering.cpp updated: 1.70 -> 1.71
X86ISelLowering.h updated: 1.22 -> 1.23
X86InstrInfo.td updated: 1.224 -> 1.225
X86Subtarget.h updated: 1.9 -> 1.10
---
Log message:
* Fix 80-column violations
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.
---
Diffs of the changes: (+67 -27)
X86.td | 32 ++++++++++++++++----------------
X86ISelLowering.cpp | 52 +++++++++++++++++++++++++++++++++++++++++++++-------
X86ISelLowering.h | 2 ++
X86InstrInfo.td | 2 +-
X86Subtarget.h | 6 +++---
5 files changed, 67 insertions(+), 27 deletions(-)
Index: llvm/lib/Target/X86/X86.td
diff -u llvm/lib/Target/X86/X86.td:1.20 llvm/lib/Target/X86/X86.td:1.21
--- llvm/lib/Target/X86/X86.td:1.20 Sat Jan 28 21:45:35 2006
+++ llvm/lib/Target/X86/X86.td Tue Jan 31 13:43:35 2006
@@ -24,7 +24,7 @@
"Enable 64-bit instructions">;
def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
"Enable MMX instructions">;
-def FeatureSSE : SubtargetFeature<"sse", "X86SSELevel", "SSE",
+def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
"Enable SSE instructions">;
def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
"Enable SSE2 instructions">;
@@ -50,16 +50,16 @@
def : Proc<"i686", []>;
def : Proc<"pentiumpro", []>;
def : Proc<"pentium2", [FeatureMMX]>;
-def : Proc<"pentium3", [FeatureMMX, FeatureSSE]>;
-def : Proc<"pentium-m", [FeatureMMX, FeatureSSE, FeatureSSE2]>;
-def : Proc<"pentium4", [FeatureMMX, FeatureSSE, FeatureSSE2]>;
-def : Proc<"x86-64", [FeatureMMX, FeatureSSE, FeatureSSE2,
+def : Proc<"pentium3", [FeatureMMX, FeatureSSE1]>;
+def : Proc<"pentium-m", [FeatureMMX, FeatureSSE1, FeatureSSE2]>;
+def : Proc<"pentium4", [FeatureMMX, FeatureSSE1, FeatureSSE2]>;
+def : Proc<"x86-64", [FeatureMMX, FeatureSSE1, FeatureSSE2,
Feature64Bit]>;
-def : Proc<"yonah", [FeatureMMX, FeatureSSE, FeatureSSE2,
+def : Proc<"yonah", [FeatureMMX, FeatureSSE1, FeatureSSE2,
FeatureSSE3]>;
-def : Proc<"prescott", [FeatureMMX, FeatureSSE, FeatureSSE2,
+def : Proc<"prescott", [FeatureMMX, FeatureSSE1, FeatureSSE2,
FeatureSSE3]>;
-def : Proc<"nocona", [FeatureMMX, FeatureSSE, FeatureSSE2,
+def : Proc<"nocona", [FeatureMMX, FeatureSSE1, FeatureSSE2,
FeatureSSE3, Feature64Bit]>;
def : Proc<"k6", [FeatureMMX]>;
@@ -67,25 +67,25 @@
def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>;
def : Proc<"athlon", [FeatureMMX, Feature3DNow, Feature3DNowA]>;
def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNow, Feature3DNowA]>;
-def : Proc<"athlon-4", [FeatureMMX, FeatureSSE, Feature3DNow,
+def : Proc<"athlon-4", [FeatureMMX, FeatureSSE1, Feature3DNow,
Feature3DNowA]>;
-def : Proc<"athlon-xp", [FeatureMMX, FeatureSSE, Feature3DNow,
+def : Proc<"athlon-xp", [FeatureMMX, FeatureSSE1, Feature3DNow,
Feature3DNowA]>;
-def : Proc<"athlon-mp", [FeatureMMX, FeatureSSE, Feature3DNow,
+def : Proc<"athlon-mp", [FeatureMMX, FeatureSSE1, Feature3DNow,
Feature3DNowA]>;
-def : Proc<"k8", [FeatureMMX, FeatureSSE, FeatureSSE2,
+def : Proc<"k8", [FeatureMMX, FeatureSSE1, FeatureSSE2,
Feature3DNow, Feature3DNowA, Feature64Bit]>;
-def : Proc<"opteron", [FeatureMMX, FeatureSSE, FeatureSSE2,
+def : Proc<"opteron", [FeatureMMX, FeatureSSE1, FeatureSSE2,
Feature3DNow, Feature3DNowA, Feature64Bit]>;
-def : Proc<"athlon64", [FeatureMMX, FeatureSSE, FeatureSSE2,
+def : Proc<"athlon64", [FeatureMMX, FeatureSSE1, FeatureSSE2,
Feature3DNow, Feature3DNowA, Feature64Bit]>;
-def : Proc<"athlon-fx", [FeatureMMX, FeatureSSE, FeatureSSE2,
+def : Proc<"athlon-fx", [FeatureMMX, FeatureSSE1, FeatureSSE2,
Feature3DNow, Feature3DNowA, Feature64Bit]>;
def : Proc<"winchip-c6", [FeatureMMX]>;
def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>;
def : Proc<"c3", [FeatureMMX, Feature3DNow]>;
-def : Proc<"c3-2", [FeatureMMX, FeatureSSE]>;
+def : Proc<"c3-2", [FeatureMMX, FeatureSSE1]>;
//===----------------------------------------------------------------------===//
// Register File Description
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.70 llvm/lib/Target/X86/X86ISelLowering.cpp:1.71
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.70 Mon Jan 30 21:14:29 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Jan 31 13:43:35 2006
@@ -25,6 +25,7 @@
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetOptions.h"
+#include "llvm/ADT/VectorExtras.h"
using namespace llvm;
// FIXME: temporary.
@@ -564,7 +565,7 @@
Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
Ops.push_back(DAG.getConstant(0, getPointerTy()));
- SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
+ SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL :X86ISD::CALL,
RetVals, Ops);
SDOperand ResultVal;
@@ -1068,7 +1069,7 @@
// Pass register arguments as needed.
Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
- SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
+ SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL :X86ISD::CALL,
RetVals, Ops);
Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
@@ -1157,7 +1158,8 @@
/// specific condition code. It returns a false if it cannot do a direct
/// translation. X86CC is the translated CondCode. Flip is set to true if the
/// the order of comparison operands should be flipped.
-static bool translateX86CC(SDOperand CC, bool isFP, unsigned &X86CC, bool &Flip) {
+static bool translateX86CC(SDOperand CC, bool isFP, unsigned &X86CC,
+ bool &Flip) {
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
Flip = false;
X86CC = X86ISD::COND_INVALID;
@@ -1234,10 +1236,10 @@
default: assert(false && "Unexpected instr type to insert");
case X86::CMOV_FR32:
case X86::CMOV_FR64: {
- // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
- // control-flow pattern. The incoming instruction knows the destination vreg
- // to set, the condition code register to branch on, the true/false values to
- // select between, and a branch opcode to use.
+ // To "insert" a SELECT_CC instruction, we actually have to insert the
+ // diamond control-flow pattern. The incoming instruction knows the
+ // destination vreg to set, the condition code register to branch on, the
+ // true/false values to select between, and a branch opcode to use.
const BasicBlock *LLVM_BB = BB->getBasicBlock();
ilist<MachineBasicBlock>::iterator It = BB;
++It;
@@ -1957,3 +1959,39 @@
return false;
}
+
+std::vector<unsigned> X86TargetLowering::
+getRegForInlineAsmConstraint(const std::string &Constraint) const {
+ if (Constraint.size() == 1) {
+ // FIXME: not handling fp-stack yet!
+ // FIXME: not handling MMX registers yet ('y' constraint).
+ switch (Constraint[0]) { // GCC X86 Constraint Letters
+ default: break; // Unknown constriant letter
+ case 'r': // GENERAL_REGS
+ case 'R': // LEGACY_REGS
+ return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX,
+ X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0);
+ case 'l': // INDEX_REGS
+ return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX,
+ X86::ESI, X86::EDI, X86::EBP, 0);
+ case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
+ case 'Q': // Q_REGS
+ return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0);
+ case 'x': // SSE_REGS if SSE1 allowed
+ if (Subtarget->hasSSE1())
+ return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
+ X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
+ 0);
+ return std::vector<unsigned>();
+ case 'Y': // SSE_REGS if SSE2 allowed
+ if (Subtarget->hasSSE2())
+ return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
+ X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
+ 0);
+ return std::vector<unsigned>();
+ }
+ }
+
+ // Handle explicit register names.
+ return TargetLowering::getRegForInlineAsmConstraint(Constraint);
+}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.22 llvm/lib/Target/X86/X86ISelLowering.h:1.23
--- llvm/lib/Target/X86/X86ISelLowering.h:1.22 Mon Jan 30 21:14:29 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Tue Jan 31 13:43:35 2006
@@ -216,6 +216,8 @@
SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
+ std::vector<unsigned>
+ getRegForInlineAsmConstraint(const std::string &Constraint) const;
private:
// C Calling Convention implementation.
std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.224 llvm/lib/Target/X86/X86InstrInfo.td:1.225
--- llvm/lib/Target/X86/X86InstrInfo.td:1.224 Mon Jan 30 21:14:29 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Tue Jan 31 13:43:35 2006
@@ -192,7 +192,7 @@
//===----------------------------------------------------------------------===//
// X86 Instruction Predicate Definitions.
-def HasSSE1 : Predicate<"Subtarget->hasSSE()">;
+def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
def FPStack : Predicate<"!Subtarget->hasSSE2()">;
Index: llvm/lib/Target/X86/X86Subtarget.h
diff -u llvm/lib/Target/X86/X86Subtarget.h:1.9 llvm/lib/Target/X86/X86Subtarget.h:1.10
--- llvm/lib/Target/X86/X86Subtarget.h:1.9 Fri Jan 27 02:10:46 2006
+++ llvm/lib/Target/X86/X86Subtarget.h Tue Jan 31 13:43:35 2006
@@ -24,14 +24,14 @@
class X86Subtarget : public TargetSubtarget {
protected:
enum X86SSEEnum {
- NoMMXSSE, MMX, SSE, SSE2, SSE3
+ NoMMXSSE, MMX, SSE1, SSE2, SSE3
};
enum X863DNowEnum {
NoThreeDNow, ThreeDNow, ThreeDNowA
};
- /// X86SSELevel - MMX, SSE, SSE2, SSE3, or none supported.
+ /// X86SSELevel - MMX, SSE1, SSE2, SSE3, or none supported.
X86SSEEnum X86SSELevel;
/// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
@@ -76,7 +76,7 @@
bool is64Bit() const { return Is64Bit; }
bool hasMMX() const { return X86SSELevel >= MMX; }
- bool hasSSE() const { return X86SSELevel >= SSE; }
+ bool hasSSE1() const { return X86SSELevel >= SSE1; }
bool hasSSE2() const { return X86SSELevel >= SSE2; }
bool hasSSE3() const { return X86SSELevel >= SSE3; }
bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
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