[llvm-commits] CVS: llvm/lib/Target/SparcV8/README.txt
Chris Lattner
lattner at cs.uiuc.edu
Mon Jan 30 23:37:32 PST 2006
Changes in directory llvm/lib/Target/SparcV8:
README.txt updated: 1.43 -> 1.44
---
Log message:
add a note
---
Diffs of the changes: (+29 -0)
README.txt | 29 +++++++++++++++++++++++++++++
1 files changed, 29 insertions(+)
Index: llvm/lib/Target/SparcV8/README.txt
diff -u llvm/lib/Target/SparcV8/README.txt:1.43 llvm/lib/Target/SparcV8/README.txt:1.44
--- llvm/lib/Target/SparcV8/README.txt:1.43 Sun Jan 29 23:35:57 2006
+++ llvm/lib/Target/SparcV8/README.txt Tue Jan 31 01:37:20 2006
@@ -7,4 +7,33 @@
* We can fold small constant offsets into the %hi/%lo references to constant
pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
+* Emit the 'Branch on Integer Register with Prediction' instructions. It's
+ not clear how to write a pattern for this though:
+
+float %t1(int %a, int* %p) {
+ %C = seteq int %a, 0
+ br bool %C, label %T, label %F
+T:
+ store int 123, int* %p
+ br label %F
+F:
+ ret float undef
+}
+
+codegens to this:
+
+t1:
+ save -96, %o6, %o6
+1) subcc %i0, 0, %l0
+1) bne .LBBt1_2 ! F
+ nop
+.LBBt1_1: ! T
+ or %g0, 123, %l0
+ st %l0, [%i1]
+.LBBt1_2: ! F
+ restore %g0, %g0, %g0
+ retl
+ nop
+
+1) should be replaced with a brz in V9 mode.
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