[llvm-commits] CVS: llvm/lib/Target/SparcV8/README.txt SparcV8ISelDAGToDAG.cpp SparcV8InstrInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/SparcV8:

README.txt updated: 1.42 -> 1.43
SparcV8ISelDAGToDAG.cpp updated: 1.65 -> 1.66
SparcV8InstrInfo.td updated: 1.105 -> 1.106
---
Log message:

First step towards V9 instructions in the V8 backend, two conditional move
patterns.  This allows emission of this code:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        move %icc, %i0, %i2
        or %g0, %i2, %i0
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        be .LBBt1_2     ! 
        nop
.LBBt1_1:       ! 
        or %g0, %i2, %i0
.LBBt1_2:       ! 
        restore %g0, %g0, %g0
        retl
        nop

for this:

int %t1(int %a, int %b, int %c) {
        %tmp.2 = seteq int %a, %b
        %tmp3 = select bool %tmp.2, int %a, int %c
        ret int %tmp3
}



---
Diffs of the changes:  (+44 -7)

 README.txt              |    7 +------
 SparcV8ISelDAGToDAG.cpp |    8 +++++++-
 SparcV8InstrInfo.td     |   36 ++++++++++++++++++++++++++++++++++++
 3 files changed, 44 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/SparcV8/README.txt
diff -u llvm/lib/Target/SparcV8/README.txt:1.42 llvm/lib/Target/SparcV8/README.txt:1.43
--- llvm/lib/Target/SparcV8/README.txt:1.42	Fri Dec 23 01:37:47 2005
+++ llvm/lib/Target/SparcV8/README.txt	Sun Jan 29 23:35:57 2006
@@ -1,10 +1,4 @@
 
-Meta TODO list:
-1. Create a new DAG -> DAG instruction selector, by adding patterns to the
-   instructions.
-2. ???
-3. profit!
-
 To-do
 -----
 
@@ -12,4 +6,5 @@
   address all of the time.
 * We can fold small constant offsets into the %hi/%lo references to constant
   pool addresses as well.
+* When in V9 mode, register allocate %icc[0-3].
 


Index: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.65 llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.66
--- llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.65	Sun Jan 29 22:34:44 2006
+++ llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp	Sun Jan 29 23:35:57 2006
@@ -850,9 +850,15 @@
 namespace {
 class SparcV8DAGToDAGISel : public SelectionDAGISel {
   SparcV8TargetLowering V8Lowering;
+
+  /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
+  /// make the right decision when generating code for different targets.
+  const SparcV8Subtarget &Subtarget;
 public:
   SparcV8DAGToDAGISel(TargetMachine &TM)
-    : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
+    : SelectionDAGISel(V8Lowering), V8Lowering(TM),
+      Subtarget(TM.getSubtarget<SparcV8Subtarget>()) {
+  }
 
   SDOperand Select(SDOperand Op);
 


Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
diff -u llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.105 llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.106
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.105	Fri Jan 27 17:30:03 2006
+++ llvm/lib/Target/SparcV8/SparcV8InstrInfo.td	Sun Jan 29 23:35:57 2006
@@ -18,6 +18,23 @@
 include "SparcV8InstrFormats.td"
 
 //===----------------------------------------------------------------------===//
+// Feature predicates.
+//===----------------------------------------------------------------------===//
+
+// HasV9 - This predicate is true when the target processor supports V9
+// instructions.  Note that the machine may be running in 32-bit mode.
+def HasV9   : Predicate<"Subtarget.isV9()">;
+
+// HasVIS - This is true when the target processor has VIS extensions.
+def HasVIS : Predicate<"Subtarget.isVIS()">;
+
+// UseDeprecatedInsts - This predicate is true when the target processor is a
+// V8, or when it is V9 but the V8 deprecated instructions are efficient enough
+// to use when appropriate.  In either of these cases, the instruction selector
+// will pick deprecated instructions.
+def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
+
+//===----------------------------------------------------------------------===//
 // Instruction Pattern Stuff
 //===----------------------------------------------------------------------===//
 
@@ -168,6 +185,7 @@
                                              imm:$Cond, FCC))]>;
 }
 
+
 // Section A.3 - Synthetic Instructions, p. 85
 // special cases of JMPL:
 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
@@ -706,6 +724,24 @@
                   "fcmpd $src1, $src2\n\tnop",
                   [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
 
+
+//===----------------------------------------------------------------------===//
+// V9 Instructions
+//===----------------------------------------------------------------------===//
+
+// V9 Conditional Moves.
+let Predicates = [HasV9], isTwoAddress = 1 in {
+  // FIXME: Add instruction encodings for the JIT some day.
+  def MOVNE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
+                     "movne %icc, $F, $dst",
+                     [(set IntRegs:$dst,
+                           (V8selecticc IntRegs:$F, IntRegs:$T, 22, ICC))]>;
+  def MOVEQ : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
+                     "move %icc, $F, $dst",
+                     [(set IntRegs:$dst,
+                           (V8selecticc IntRegs:$F, IntRegs:$T, 17, ICC))]>;
+}
+
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //===----------------------------------------------------------------------===//