[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.277 -> 1.278
SelectionDAG.cpp updated: 1.244 -> 1.245
SelectionDAGISel.cpp updated: 1.137 -> 1.138
---
Log message:

initial selectiondag support for new INLINEASM node.  Note that inline asms
with outputs or inputs are not supported yet. :)



---
Diffs of the changes:  (+74 -1)

 LegalizeDAG.cpp      |   22 ++++++++++++++++++++++
 SelectionDAG.cpp     |    3 ++-
 SelectionDAGISel.cpp |   50 ++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 74 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.277 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.278
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.277	Wed Jan 25 12:21:52 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Thu Jan 26 16:24:51 2006
@@ -881,6 +881,28 @@
     AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
     return Op.ResNo ? Tmp2 : Tmp1;
   }
+  case ISD::INLINEASM:
+    Tmp1 = LegalizeOp(Node->getOperand(0));   // Legalize Chain.
+    Tmp2 = Node->getOperand(Node->getNumOperands()-1);
+    if (Tmp2.getValueType() != MVT::Flag)     // Legalize Flag if it exists.
+      Tmp2 = Tmp3 = SDOperand(0, 0);
+    else
+      Tmp3 = LegalizeOp(Tmp2);
+    
+    if (Tmp1 != Node->getOperand(0) || Tmp2 != Tmp3) {
+      std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
+      Ops[0] = Tmp1;
+      Ops.back() = Tmp3;
+      std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
+      Result = DAG.getNode(ISD::INLINEASM, VTs, Ops);
+    } else {
+      Result = SDOperand(Node, 0);
+    }
+      
+    // INLINE asm returns a chain and flag, make sure to add both to the map.
+    AddLegalizedOperand(SDOperand(Node, 0), Result);
+    AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+    return Result.getValue(Op.ResNo);
   case ISD::TAILCALL:
   case ISD::CALL: {
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.244 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.245
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.244	Wed Jan 25 12:21:52 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Thu Jan 26 16:24:51 2006
@@ -2028,7 +2028,8 @@
   case ISD::CopyFromReg:   return "CopyFromReg";
   case ISD::UNDEF:         return "undef";
   case ISD::MERGE_VALUES:  return "mergevalues";
-
+  case ISD::INLINEASM:     return "inlineasm";
+    
   // Unary operators
   case ISD::FABS:   return "fabs";
   case ISD::FNEG:   return "fneg";


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.137 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.138
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.137	Wed Jan 25 12:21:52 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Thu Jan 26 16:24:51 2006
@@ -19,6 +19,7 @@
 #include "llvm/DerivedTypes.h"
 #include "llvm/Function.h"
 #include "llvm/GlobalVariable.h"
+#include "llvm/InlineAsm.h"
 #include "llvm/Instructions.h"
 #include "llvm/Intrinsics.h"
 #include "llvm/CodeGen/IntrinsicLowering.h"
@@ -468,6 +469,7 @@
   void visitStore(StoreInst &I);
   void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
   void visitCall(CallInst &I);
+  void visitInlineAsm(CallInst &I);
   const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
 
   void visitVAStart(CallInst &I);
@@ -1122,6 +1124,9 @@
           }
         }
       }
+  } else if (isa<InlineAsm>(I.getOperand(0))) {
+    visitInlineAsm(I);
+    return;
   }
 
   SDOperand Callee;
@@ -1148,6 +1153,51 @@
   DAG.setRoot(Result.second);
 }
 
+/// visitInlineAsm - Handle a call to an InlineAsm object.
+///
+void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
+  InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
+  
+  SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
+                                                 MVT::Other);
+
+  // Note, we treat inline asms both with and without side-effects as the same.
+  // If an inline asm doesn't have side effects and doesn't access memory, we
+  // could not choose to not chain it.
+  bool hasSideEffects = IA->hasSideEffects();
+
+  std::vector<std::pair<InlineAsm::ConstraintPrefix, std::string> > 
+    Constraints = IA->ParseConstraints();
+
+  
+  /// AsmNodeOperands - A list of pairs.  The first element is a register, the
+  /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
+  /// if it is a def of that register.
+  std::vector<SDOperand> AsmNodeOperands;
+  AsmNodeOperands.push_back(SDOperand());  // reserve space for input chain
+  AsmNodeOperands.push_back(AsmStr);
+  
+  SDOperand Chain = getRoot();
+  SDOperand Flag;
+  
+  // FIXME: input copies.
+  
+  // Finish up input operands.
+  AsmNodeOperands[0] = Chain;
+  if (Flag.Val) AsmNodeOperands.push_back(Flag);
+  
+  std::vector<MVT::ValueType> VTs;
+  VTs.push_back(MVT::Other);
+  VTs.push_back(MVT::Flag);
+  Chain = DAG.getNode(ISD::INLINEASM, VTs, AsmNodeOperands);
+  Flag = Chain.getValue(1);
+
+  // FIXME: Copies out of registers here, setValue(CI).
+  
+  DAG.setRoot(Chain);
+}
+
+
 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
   SDOperand Src = getValue(I.getOperand(0));