[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

[Evan Cheng]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.135 -> 1.136
---
Log message:

If scheduler choice is the default (-sched=default), use target scheduling
preference to determine which scheduler to use. SchedulingForLatency ==
Breadth first; SchedulingForRegPressure == bottom up register reduction list
scheduler.


---
Diffs of the changes:  (+10 -2)

 SelectionDAGISel.cpp |   12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.135 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.136
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.135	Mon Jan 23 07:34:04 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Wed Jan 25 03:12:57 2006
@@ -59,8 +59,10 @@
   ISHeuristic(
     "sched",
     cl::desc("Choose scheduling style"),
-    cl::init(noScheduling),
+    cl::init(defaultScheduling),
     cl::values(
+      clEnumValN(defaultScheduling, "default",
+                 "Target preferred scheduling style"),
       clEnumValN(noScheduling, "none",
                  "No scheduling: breadth first sequencing"),
       clEnumValN(simpleScheduling, "simple",
@@ -69,7 +71,7 @@
       clEnumValN(simpleNoItinScheduling, "simple-noitin",
                  "Simple two pass scheduling: Same as simple "
                  "except using generic latency"),
-      clEnumValN(listSchedulingBURR, "list-BURR",
+      clEnumValN(listSchedulingBURR, "list-burr",
                  "Bottom up register reduction list scheduling"),
       clEnumValEnd));
 } // namespace
@@ -1772,6 +1774,12 @@
 
   switch (ISHeuristic) {
   default: assert(0 && "Unrecognized scheduling heuristic");
+  case defaultScheduling:
+    if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
+      SL = createSimpleDAGScheduler(noScheduling, DAG, BB);
+    else /* TargetLowering::SchedulingForRegPressure */
+      SL = createBURRListDAGScheduler(DAG, BB);
+    break;
   case noScheduling:
   case simpleScheduling:
   case simpleNoItinScheduling: