[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp

[Duraid Madina]

Changes in directory llvm/lib/Target/IA64:

IA64ISelDAGToDAG.cpp updated: 1.26 -> 1.27
IA64ISelLowering.cpp updated: 1.23 -> 1.24
---
Log message:


fix sext breakage: now we correctly deal with functions that return
int vs uint



---
Diffs of the changes:  (+5 -1)

 IA64ISelDAGToDAG.cpp |    2 +-
 IA64ISelLowering.cpp |    4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.26 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.27
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.26	Thu Jan 19 21:40:25 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp	Fri Jan 20 10:10:05 2006
@@ -494,7 +494,7 @@
 */
 
   case ISD::LOAD:
-  case ISD::EXTLOAD:
+  case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
   case ISD::ZEXTLOAD: {
     SDOperand Chain = Select(N->getOperand(0));
     SDOperand Address = Select(N->getOperand(1));


Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.23 llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.24
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.23	Thu Jan 19 02:31:51 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp	Fri Jan 20 10:10:05 2006
@@ -475,6 +475,8 @@
     switch (RetTyVT) {
     default: assert(0 && "Unknown value type to return!");
     case MVT::i1: { // bools are just like other integers (returned in r8)
+      // we *could* fall through to the truncate below, but this saves a
+      // few redundant predicate ops
       SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
       InFlag = boolInR8.getValue(2);
       Chain = boolInR8.getValue(1);
@@ -492,8 +494,10 @@
       Chain = RetVal.getValue(1);
       
       // keep track of whether it is sign or zero extended (todo: bools?)
+/* XXX
       RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
                            MVT::i64, RetVal, DAG.getValueType(RetTyVT));
+*/
       RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
       break;
     case MVT::i64: