[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Reid Spencer
reid at x10sys.com
Mon Jan 16 13:12:53 PST 2006
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.125 -> 1.126
---
Log message:
For PR411: http://llvm.cs.uiuc.edu/PR411 :
This patch is an incremental step towards supporting a flat symbol table.
It de-overloads the intrinsic functions by providing type-specific intrinsics
and arranging for automatically upgrading from the old overloaded name to
the new non-overloaded name. Specifically:
llvm.isunordered -> llvm.isunordered.f32, llvm.isunordered.f64
llvm.sqrt -> llvm.sqrt.f32, llvm.sqrt.f64
llvm.ctpop -> llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64
llvm.ctlz -> llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64
llvm.cttz -> llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64
New code should not use the overloaded intrinsic names. Warnings will be
emitted if they are used.
---
Diffs of the changes: (+16 -5)
SelectionDAGISel.cpp | 21 ++++++++++++++++-----
1 files changed, 16 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.125 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.126
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.125 Fri Jan 13 21:18:27 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Jan 16 15:12:35 2006
@@ -963,12 +963,14 @@
setValue(&I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType())));
return 0;
- case Intrinsic::isunordered:
+ case Intrinsic::isunordered_f32:
+ case Intrinsic::isunordered_f64:
setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
getValue(I.getOperand(2)), ISD::SETUO));
return 0;
- case Intrinsic::sqrt:
+ case Intrinsic::sqrt_f32:
+ case Intrinsic::sqrt_f64:
setValue(&I, DAG.getNode(ISD::FSQRT,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
@@ -996,17 +998,26 @@
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
- case Intrinsic::cttz:
+ case Intrinsic::cttz_i8:
+ case Intrinsic::cttz_i16:
+ case Intrinsic::cttz_i32:
+ case Intrinsic::cttz_i64:
setValue(&I, DAG.getNode(ISD::CTTZ,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
- case Intrinsic::ctlz:
+ case Intrinsic::ctlz_i8:
+ case Intrinsic::ctlz_i16:
+ case Intrinsic::ctlz_i32:
+ case Intrinsic::ctlz_i64:
setValue(&I, DAG.getNode(ISD::CTLZ,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
- case Intrinsic::ctpop:
+ case Intrinsic::ctpop_i8:
+ case Intrinsic::ctpop_i16:
+ case Intrinsic::ctpop_i32:
+ case Intrinsic::ctpop_i64:
setValue(&I, DAG.getNode(ISD::CTPOP,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
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