[llvm-commits] CVS: llvm/lib/Target/X86/README.txt X86ISelLowering.cpp X86ISelLowering.h X86ISelPattern.cpp X86InstrInfo.td
Evan Cheng
evan.cheng at apple.com
Thu Jan 12 14:54:33 PST 2006
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.20 -> 1.21
X86ISelLowering.cpp updated: 1.33 -> 1.34
X86ISelLowering.h updated: 1.14 -> 1.15
X86ISelPattern.cpp updated: 1.194 -> 1.195
X86InstrInfo.td updated: 1.201 -> 1.202
---
Log message:
Fix sint_to_fp (fild*) support.
---
Diffs of the changes: (+61 -42)
README.txt | 15 ++++++++++-----
X86ISelLowering.cpp | 37 +++++++++++++++++++++++++------------
X86ISelLowering.h | 12 ++++++------
X86ISelPattern.cpp | 4 ++--
X86InstrInfo.td | 35 ++++++++++++++++++-----------------
5 files changed, 61 insertions(+), 42 deletions(-)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.20 llvm/lib/Target/X86/README.txt:1.21
--- llvm/lib/Target/X86/README.txt:1.20 Sat Dec 17 00:54:43 2005
+++ llvm/lib/Target/X86/README.txt Thu Jan 12 16:54:21 2006
@@ -31,16 +31,12 @@
//===---------------------------------------------------------------------===//
-Need to add support for rotate instructions.
-
-//===---------------------------------------------------------------------===//
-
Some targets (e.g. athlons) prefer freep to fstp ST(0):
http://gcc.gnu.org/ml/gcc-patches/2004-04/msg00659.html
//===---------------------------------------------------------------------===//
-This should use faddi on chips where it is profitable:
+This should use fiadd on chips where it is profitable:
double foo(double P, int *I) { return P+*I; }
//===---------------------------------------------------------------------===//
@@ -107,3 +103,12 @@
Leave any_extend as pseudo instruction and hint to register
allocator. Delay codegen until post register allocation.
+
+//===---------------------------------------------------------------------===//
+
+Add a target specific hook to DAG combiner to handle SINT_TO_FP and
+FP_TO_SINT when the source operand is already in memory.
+
+//===---------------------------------------------------------------------===//
+
+Check if load folding would add a cycle in the dag.
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.33 llvm/lib/Target/X86/X86ISelLowering.cpp:1.34
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.33 Thu Jan 12 02:27:59 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Jan 12 16:54:21 2006
@@ -194,6 +194,11 @@
// Set up the FP register classes.
addRegisterClass(MVT::f64, X86::RFPRegisterClass);
+ if (X86DAGIsel) {
+ setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
+ }
+
if (!UnsafeFPMath) {
setOperationAction(ISD::FSIN , MVT::f64 , Expand);
setOperationAction(ISD::FCOS , MVT::f64 , Expand);
@@ -1404,22 +1409,30 @@
}
case ISD::SINT_TO_FP: {
assert(Op.getValueType() == MVT::f64 &&
- Op.getOperand(0).getValueType() == MVT::i64 &&
+ Op.getOperand(0).getValueType() <= MVT::i64 &&
+ Op.getOperand(0).getValueType() >= MVT::i16 &&
"Unknown SINT_TO_FP to lower!");
- // We lower sint64->FP into a store to a temporary stack slot, followed by a
- // FILD64m node.
+
+ SDOperand Result;
+ MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
+ unsigned Size = MVT::getSizeInBits(SrcVT)/8;
MachineFunction &MF = DAG.getMachineFunction();
- int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
+ int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
- SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
- Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL));
- std::vector<MVT::ValueType> RTs;
- RTs.push_back(MVT::f64);
- RTs.push_back(MVT::Other);
+ SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other,
+ DAG.getEntryNode(), Op.getOperand(0),
+ StackSlot, DAG.getSrcValue(NULL));
+
+ // Build the FILD
+ std::vector<MVT::ValueType> Tys;
+ Tys.push_back(MVT::f64);
+ Tys.push_back(MVT::Flag);
std::vector<SDOperand> Ops;
- Ops.push_back(Store);
+ Ops.push_back(Chain);
Ops.push_back(StackSlot);
- return DAG.getNode(X86ISD::FILD64m, RTs, Ops);
+ Ops.push_back(DAG.getValueType(SrcVT));
+ Result = DAG.getNode(X86ISD::FILD, Tys, Ops);
+ return Result;
}
case ISD::FP_TO_SINT: {
assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
@@ -1749,7 +1762,7 @@
case X86ISD::SBB: return "X86ISD::SBB";
case X86ISD::SHLD: return "X86ISD::SHLD";
case X86ISD::SHRD: return "X86ISD::SHRD";
- case X86ISD::FILD64m: return "X86ISD::FILD64m";
+ case X86ISD::FILD: return "X86ISD::FILD";
case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.14 llvm/lib/Target/X86/X86ISelLowering.h:1.15
--- llvm/lib/Target/X86/X86ISelLowering.h:1.14 Wed Jan 11 16:15:48 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Thu Jan 12 16:54:21 2006
@@ -40,16 +40,16 @@
SHLD,
SHRD,
- /// FILD64m - This instruction implements SINT_TO_FP with a
- /// 64-bit source in memory and a FP reg result. This corresponds to
- /// the X86::FILD64m instruction. It has two inputs (token chain and
- /// address) and two outputs (FP value and token chain).
- FILD64m,
+ /// FILD - This instruction implements SINT_TO_FP with the integer source
+ /// in memory and FP reg result. This corresponds to the X86::FILD*m
+ /// instructions. It has three inputs (token chain, address, and source
+ /// type) and two outputs (FP value and token chain).
+ FILD,
/// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
/// integer destination in memory and a FP reg source. This corresponds
/// to the X86::FIST*m instructions and the rounding mode change stuff. It
- /// has two inputs (token chain and address) and two outputs (FP value and
+ /// has two inputs (token chain and address) and two outputs (int value and
/// token chain).
FP_TO_INT16_IN_MEM,
FP_TO_INT32_IN_MEM,
Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.194 llvm/lib/Target/X86/X86ISelPattern.cpp:1.195
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.194 Wed Jan 11 16:15:48 2006
+++ llvm/lib/Target/X86/X86ISelPattern.cpp Thu Jan 12 16:54:21 2006
@@ -2259,7 +2259,7 @@
addFullAddress(BuildMI(BB, Opc, 4, Result), AM);
}
return Result;
- case X86ISD::FILD64m:
+ case X86ISD::FILD:
// Make sure we generate both values.
assert(Result != 1 && N.getValueType() == MVT::f64);
if (!ExprMap.insert(std::make_pair(N.getValue(1), 1)).second)
@@ -3301,7 +3301,7 @@
SelectExpr(N);
return;
case ISD::CopyFromReg:
- case X86ISD::FILD64m:
+ case X86ISD::FILD:
ExprMap.erase(N);
SelectExpr(N.getValue(0));
return;
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.201 llvm/lib/Target/X86/X86InstrInfo.td:1.202
--- llvm/lib/Target/X86/X86InstrInfo.td:1.201 Thu Jan 12 13:36:31 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Thu Jan 12 16:54:21 2006
@@ -50,7 +50,8 @@
SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
-def SDTX86Fild64m : SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisPtrTy<1>]>;
+def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisPtrTy<1>,
+ SDTCisVT<2, OtherVT>]>;
def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
@@ -99,7 +100,7 @@
[SDNPHasChain]>;
def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
[SDNPHasChain]>;
-def X86fild64m : SDNode<"X86ISD::FILD64m", SDTX86Fild64m,
+def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
[SDNPHasChain]>;
def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
@@ -2707,50 +2708,50 @@
// FIXME: Implement these when we have a dag-dag isel!
def FpIADD16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
[(set RFP:$dst, (fadd RFP:$src1,
- (sint_to_fp (loadi16 addr:$src2))))]>;
+ (X86fild addr:$src2, i16)))]>;
// ST(0) = ST(0) + [mem16int]
def FpIADD32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
[(set RFP:$dst, (fadd RFP:$src1,
- (sint_to_fp (loadi32 addr:$src2))))]>;
+ (X86fild addr:$src2, i32)))]>;
// ST(0) = ST(0) + [mem32int]
def FpIMUL16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
[(set RFP:$dst, (fmul RFP:$src1,
- (sint_to_fp (loadi16 addr:$src2))))]>;
+ (X86fild addr:$src2, i16)))]>;
// ST(0) = ST(0) * [mem16int]
def FpIMUL32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
[(set RFP:$dst, (fmul RFP:$src1,
- (sint_to_fp (loadi32 addr:$src2))))]>;
+ (X86fild addr:$src2, i32)))]>;
// ST(0) = ST(0) * [mem32int]
def FpISUB16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
[(set RFP:$dst, (fsub RFP:$src1,
- (sint_to_fp (loadi16 addr:$src2))))]>;
+ (X86fild addr:$src2, i16)))]>;
// ST(0) = ST(0) - [mem16int]
def FpISUB32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
[(set RFP:$dst, (fsub RFP:$src1,
- (sint_to_fp (loadi32 addr:$src2))))]>;
+ (X86fild addr:$src2, i32)))]>;
// ST(0) = ST(0) - [mem32int]
def FpISUBR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
- [(set RFP:$dst, (fsub (sint_to_fp (loadi16 addr:$src2)),
+ [(set RFP:$dst, (fsub (X86fild addr:$src2, i16),
RFP:$src1))]>;
// ST(0) = [mem16int] - ST(0)
def FpISUBR32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
- [(set RFP:$dst, (fsub (sint_to_fp (loadi32 addr:$src2)),
+ [(set RFP:$dst, (fsub (X86fild addr:$src2, i32),
RFP:$src1))]>;
// ST(0) = [mem32int] - ST(0)
def FpIDIV16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
[(set RFP:$dst, (fdiv RFP:$src1,
- (sint_to_fp (loadi16 addr:$src2))))]>;
+ (X86fild addr:$src2, i16)))]>;
// ST(0) = ST(0) / [mem16int]
def FpIDIV32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
[(set RFP:$dst, (fdiv RFP:$src1,
- (sint_to_fp (loadi32 addr:$src2))))]>;
+ (X86fild addr:$src2, i32)))]>;
// ST(0) = ST(0) / [mem32int]
def FpIDIVR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
- [(set RFP:$dst, (fdiv (sint_to_fp (loadi16 addr:$src2)),
+ [(set RFP:$dst, (fdiv (X86fild addr:$src2, i16),
RFP:$src1))]>;
// ST(0) = [mem16int] / ST(0)
def FpIDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
- [(set RFP:$dst, (fdiv (sint_to_fp (loadi32 addr:$src2)),
+ [(set RFP:$dst, (fdiv (X86fild addr:$src2, i32),
RFP:$src1))]>;
// ST(0) = [mem32int] / ST(0)
@@ -2863,11 +2864,11 @@
def FpLD64m : FpI<(ops RFP:$dst, f64mem:$src), ZeroArgFP,
[(set RFP:$dst, (loadf64 addr:$src))]>;
def FpILD16m : FpI<(ops RFP:$dst, i16mem:$src), ZeroArgFP,
- [(set RFP:$dst, (sint_to_fp (loadi16 addr:$src)))]>;
+ [(set RFP:$dst, (X86fild addr:$src, i16))]>;
def FpILD32m : FpI<(ops RFP:$dst, i32mem:$src), ZeroArgFP,
- [(set RFP:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
+ [(set RFP:$dst, (X86fild addr:$src, i32))]>;
def FpILD64m : FpI<(ops RFP:$dst, i64mem:$src), ZeroArgFP,
- [(set RFP:$dst, (X86fild64m addr:$src))]>;
+ [(set RFP:$dst, (X86fild addr:$src, i64))]>;
def FpST32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP,
[(truncstore RFP:$src, addr:$op, f32)]>;
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