[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp
Nate Begeman
natebegeman at mac.com
Wed Jan 11 13:21:17 PST 2006
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.79 -> 1.80
LegalizeDAG.cpp updated: 1.258 -> 1.259
SelectionDAG.cpp updated: 1.235 -> 1.236
---
Log message:
Add bswap, rotl, and rotr nodes
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl
Targets should add rotl/rotr patterns if they have them
---
Diffs of the changes: (+65 -2)
DAGCombiner.cpp | 38 ++++++++++++++++++++++++++++++++++++--
LegalizeDAG.cpp | 18 ++++++++++++++++++
SelectionDAG.cpp | 11 +++++++++++
3 files changed, 65 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.79 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.80
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.79 Thu Jan 5 19:56:02 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jan 11 15:21:00 2006
@@ -1133,8 +1133,6 @@
N1),
DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
}
-
-
// fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
@@ -1180,6 +1178,42 @@
WorkList.push_back(ORNode.Val);
return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
}
+ // canonicalize shl to left side in a shl/srl pair, to match rotate
+ if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
+ std::swap(N0, N1);
+ // check for rotl, rotr
+ if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
+ N0.getOperand(0) == N1.getOperand(0) &&
+ TLI.isOperationLegal(ISD::ROTL, VT)) {
+ // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
+ if (N0.getOperand(1).getOpcode() == ISD::Constant &&
+ N1.getOperand(1).getOpcode() == ISD::Constant) {
+ uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
+ uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
+ if ((c1val + c2val) == OpSizeInBits)
+ return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
+ }
+ // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
+ if (N1.getOperand(1).getOpcode() == ISD::SUB &&
+ N0.getOperand(1) == N1.getOperand(1).getOperand(1))
+ if (ConstantSDNode *SUBC =
+ dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
+ if (SUBC->getValue() == OpSizeInBits)
+ return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
+ // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
+ if (N0.getOperand(1).getOpcode() == ISD::SUB &&
+ N1.getOperand(1) == N0.getOperand(1).getOperand(1))
+ if (ConstantSDNode *SUBC =
+ dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
+ if (SUBC->getValue() == OpSizeInBits) {
+ if (TLI.isOperationLegal(ISD::ROTR, VT))
+ return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
+ N1.getOperand(1));
+ else
+ return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
+ N0.getOperand(1));
+ }
+ }
return SDOperand();
}
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.258 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.259
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.258 Tue Jan 10 13:43:26 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jan 11 15:21:00 2006
@@ -2112,6 +2112,24 @@
}
break;
+ case ISD::ROTL:
+ case ISD::ROTR:
+ Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
+ Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
+ switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
+ case TargetLowering::Custom:
+ case TargetLowering::Promote:
+ case TargetLowering::Expand:
+ assert(0 && "Cannot handle this yet!");
+ case TargetLowering::Legal:
+ if (Tmp1 != Node->getOperand(0) ||
+ Tmp2 != Node->getOperand(1))
+ Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
+ Tmp2);
+ break;
+ }
+ break;
+
case ISD::CTPOP:
case ISD::CTTZ:
case ISD::CTLZ:
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.235 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.236
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.235 Mon Jan 9 12:29:18 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jan 11 15:21:00 2006
@@ -983,6 +983,8 @@
case ISD::SHL:
case ISD::SRA:
case ISD::SRL:
+ case ISD::ROTL:
+ case ISD::ROTR:
assert(VT == N1.getValueType() &&
"Shift operators return type must be the same as their first arg");
assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) &&
@@ -1039,6 +1041,12 @@
case ISD::SHL : return getConstant(C1 << C2, VT);
case ISD::SRL : return getConstant(C1 >> C2, VT);
case ISD::SRA : return getConstant(N1C->getSignExtended() >>(int)C2, VT);
+ case ISD::ROTL :
+ return getConstant((C1 << C2) | (C1 >> (MVT::getSizeInBits(VT) - C2)),
+ VT);
+ case ISD::ROTR :
+ return getConstant((C1 >> C2) | (C1 << (MVT::getSizeInBits(VT) - C2)),
+ VT);
default: break;
}
} else { // Cannonicalize constant to RHS if commutative
@@ -1915,6 +1923,9 @@
case ISD::SHL: return "shl";
case ISD::SRA: return "sra";
case ISD::SRL: return "srl";
+ case ISD::ROTL: return "rotl";
+ case ISD::ROTR: return "rotr";
+ case ISD::BSWAP: return "bswap";
case ISD::FADD: return "fadd";
case ISD::FSUB: return "fsub";
case ISD::FMUL: return "fmul";
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