[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp

[Duraid Madina]

Changes in directory llvm/lib/Target/IA64:

IA64ISelLowering.cpp updated: 1.8 -> 1.9
---
Log message:

nasty paste-o, calls passing more than 8 arguments along were having
args >8 put into the wrong place



---
Diffs of the changes:  (+2 -2)

 IA64ISelLowering.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.8 llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.9
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.8	Thu Dec 22 07:29:14 2005
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp	Tue Dec 27 04:17:03 2005
@@ -347,12 +347,12 @@
         PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
         Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
                                      ValToStore, PtrOff, NullSV));
+        ArgOffset += ObjSize;
       }
 
       if(ValToConvert.Val) {
 	Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert)); 
       }
-      ArgOffset += ObjSize;
     }
 
   // Emit all stores, make sure they occur before any copies into physregs.
@@ -397,7 +397,7 @@
     }
   }
 
-  // next copy args into the usual places
+  // next copy args into the usual places, these are flagged
   unsigned usedFPArgs = 0;
   for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
     Chain = DAG.getCopyToReg(Chain,