[llvm-commits] Re: llvm-commits Digest, Vol 18, Issue 43

Chris Lattner sabre at nondot.org
Mon Dec 26 18:24:08 PST 2005

On Mon, 26 Dec 2005, Andrew Lenharth wrote:
>> -let isCall = 1, Defs = [R23, R24, R25, R27, R28], Uses = [R24, R25, R27]
>> in +let isCall = 1, noResults = 1, Defs = [R23, R24, R25, R27, R28], Uses =
>> [R24, R25, R27] in def JSRs : MbrForm< 0x1A, 0x01, (ops ), "jsr
>> $$23,($$27),0">; //Jump to div or rem
> things like JSR and BSR and BR and reg do return results, but I guess the only
> uses can be hidden with the use of flags.  What I really need to remove hacks
> is a way to force a results to be in a certain register that doesn't depend
> on the register allocator optionally doing the right thing.  This is easy in
> the PatternISel, but not in the DAG.  maybe like
> (ops GPRC:$RD = R27, GPRC:$RS)
> or
> let constraints = (constrain GPRC:$RD = 27) in ...
> not that there are enough hacks around this to be worth it.

I'm not sure I follow.  If this is fixed by the architecture (seems 
unlikely for alpha but...) you should be able to do something like this:

(set R27, (fooop GPRC:$in1, GPRC:$in2))

it it is not fixed by the ISA, but fixed by the architecture, you should 
handle this in the lowering code, and emit copyto/from regs.



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