[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td X86RegisterInfo.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86InstrInfo.td updated: 1.184 -> 1.185
X86RegisterInfo.cpp updated: 1.113 -> 1.114
---
Log message:

* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)


---
Diffs of the changes:  (+19 -18)

 X86InstrInfo.td     |   36 ++++++++++++++++++------------------
 X86RegisterInfo.cpp |    1 +
 2 files changed, 19 insertions(+), 18 deletions(-)


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.184 llvm/lib/Target/X86/X86InstrInfo.td:1.185
--- llvm/lib/Target/X86/X86InstrInfo.td:1.184	Fri Dec 23 01:31:11 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td	Fri Dec 23 16:14:32 2005
@@ -32,13 +32,12 @@
                                   [SDTCisVT<0, i8>, SDTCisVT<1, OtherVT>,
                                    SDTCisVT<2, FlagVT>]>;
 
-def SDTX86RetFlag : SDTypeProfile<0, 2, [SDTCisVT<0, i16>,
-                                         SDTCisVT<1, FlagVT>]>;
+def SDTX86RetFlag : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
 
 def SDTX86Fld     : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
                                          SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
 
-def SDTX86FpSet   : SDTypeProfile<1, 1, [SDTCisVT<0, FlagVT>, SDTCisFP<1>]>;
+def SDTX86FpSet   : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
 
 def X86cmp     : SDNode<"X86ISD::CMP" ,     SDTX86CmpTest,  []>;
 def X86test    : SDNode<"X86ISD::TEST",     SDTX86CmpTest,  []>;
@@ -47,7 +46,7 @@
 def X86Brcond  : SDNode<"X86ISD::BRCOND",   SDTX86BrCond,   [SDNPHasChain]>;
 def X86SetCC   : SDNode<"X86ISD::SETCC",    SDTX86SetCC,    []>;
 
-def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86RetFlag, [SDNPHasChain]>;
+def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86RetFlag,  [SDNPHasChain]>;
 
 def X86fld     : SDNode<"X86ISD::FLD",      SDTX86Fld,      [SDNPHasChain]>;
 
@@ -290,13 +289,17 @@
 //
 
 // Return instructions.
-let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in
-  def RET : I<0xC3, RawFrm, (ops), "ret", [(ret)]>;
-let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in
-  def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
+let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in {
+  // FIXME: temporary workaround for return without an incoming flag.
+  def RETVOID : I<0xC3, RawFrm, (ops), "ret", [(ret)]>;
+  let hasInFlag = 1 in {
+    def RET : I<0xC3, RawFrm, (ops), "ret", []>;
+    def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
+  }
+}
 
-def : Pat<(X86retflag 0, FLAG),        (RET)>;
-def : Pat<(X86retflag imm:$amt, FLAG), (RETI imm:$amt)>;
+def : Pat<(X86retflag 0),        (RET)>;
+def : Pat<(X86retflag imm:$amt), (RETI imm:$amt)>;
 
 // All branches are RawFrm, Void, Branch, and Terminators
 let isBranch = 1, isTerminator = 1 in
@@ -2312,17 +2315,14 @@
 }
 
 // Random Pseudo Instructions.
-def FpGETRESULT : FpPseudoI<(ops RFP:$dst), SpecialFP, // FPR = ST(0)
-                      []>;  
-def FpSETRESULT : FpPseudoI<(ops RFP:$src), SpecialFP,
-                      [(set FLAG, (X86fpset RFP:$src))]>,
-                       Imp<[], [ST0]>;  // ST(0) = FPR
+def FpGETRESULT : FpPseudoI<(ops RFP:$dst), SpecialFP, []>;     // FPR = ST(0)
+let hasOutFlag = 1 in 
+  def FpSETRESULT : FpPseudoI<(ops RFP:$src), SpecialFP,
+                    [(X86fpset RFP:$src)]>, Imp<[], [ST0]>;     // ST(0) = FPR
 
-def FpMOV       : FpI<(ops RFP:$dst, RFP:$src), SpecialFP,
-                      []>;   // f1 = fmov f2
+def FpMOV       : FpI<(ops RFP:$dst, RFP:$src), SpecialFP, []>; // f1 = fmov f2
 
 // Arithmetic
-
 // Add, Sub, Mul, Div.
 def FpADD : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
                 [(set RFP:$dst, (fadd RFP:$src1, RFP:$src2))]>;


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.113 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.114
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.113	Wed Dec 21 01:47:04 2005
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp	Fri Dec 23 16:14:32 2005
@@ -568,6 +568,7 @@
   switch (MBBI->getOpcode()) {
   case X86::RET:
   case X86::RETI:
+  case X86::RETVOID:  // FIXME: See X86InstrInfo.td
   case X86::TAILJMPd:
   case X86::TAILJMPr:
   case X86::TAILJMPm: break;  // These are ok