[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp

[Evan Cheng]

Changes in directory llvm/utils/TableGen:

DAGISelEmitter.cpp updated: 1.110 -> 1.111
---
Log message:

Allows instructions which no explicit operands. e.g. X86 RET which has but
an implicit flag operand.


---
Diffs of the changes:  (+5 -6)

 DAGISelEmitter.cpp |   11 +++++------
 1 files changed, 5 insertions(+), 6 deletions(-)


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.110 llvm/utils/TableGen/DAGISelEmitter.cpp:1.111
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.110	Tue Dec 20 23:31:05 2005
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Wed Dec 21 14:20:49 2005
@@ -1124,23 +1124,22 @@
       std::vector<Record*> Operands;
       
       CodeGenInstruction &InstInfo =Target.getInstruction(Instrs[i]->getName());
-      
-      // Doesn't even define a result?
-      if (InstInfo.OperandList.size() == 0)
-        continue;
 
+      // Note: Removed if (InstInfo.OperandList.size() == 0) continue;
+      // It's possible for some instruction, e.g. RET for X86 that only has an
+      // implicit flag operand.
       // FIXME: temporary hack...
       if (InstInfo.isReturn || InstInfo.isBranch || InstInfo.isCall ||
           InstInfo.isStore) {
         // These produce no results
-        for (unsigned j = 0, e = InstInfo.OperandList.size(); j != e; ++j)
+        for (unsigned j = 0, e = InstInfo.OperandList.size(); j < e; ++j)
           Operands.push_back(InstInfo.OperandList[j].Rec);
       } else {
         // Assume the first operand is the result.
         Results.push_back(InstInfo.OperandList[0].Rec);
       
         // The rest are inputs.
-        for (unsigned j = 1, e = InstInfo.OperandList.size(); j != e; ++j)
+        for (unsigned j = 1, e = InstInfo.OperandList.size(); j < e; ++j)
           Operands.push_back(InstInfo.OperandList[j].Rec);
       }