[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td
Evan Cheng
evan.cheng at apple.com
Mon Dec 19 15:12:51 PST 2005
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.9 -> 1.10
X86ISelLowering.h updated: 1.3 -> 1.4
X86InstrInfo.td updated: 1.172 -> 1.173
---
Log message:
X86 conditional branch support.
---
Diffs of the changes: (+53 -14)
X86ISelLowering.cpp | 21 ++++++++++++++++++++-
X86ISelLowering.h | 3 +++
X86InstrInfo.td | 43 ++++++++++++++++++++++++++++++-------------
3 files changed, 53 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.9 llvm/lib/Target/X86/X86ISelLowering.cpp:1.10
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.9 Sat Dec 17 01:18:44 2005
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Dec 19 17:12:38 2005
@@ -31,7 +31,6 @@
X86TargetLowering::X86TargetLowering(TargetMachine &TM)
: TargetLowering(TM) {
-
// Set up the TargetLowering object.
// X86 is weird, it always uses i8 for shift amounts and setcc results.
@@ -81,6 +80,9 @@
setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
+ if (X86DAGIsel) {
+ setOperationAction(ISD::BRCOND , MVT::Other, Custom);
+ }
setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
@@ -949,5 +951,22 @@
return DAG.getNode(X86ISD::CMOV, Op.getValueType(),
Op.getOperand(1), Op.getOperand(2), CC, Cond);
}
+ case ISD::BRCOND: {
+ SDOperand Chain = Op.getOperand(0);
+ SDOperand Cond = Op.getOperand(1);
+ SDOperand Dest = Op.getOperand(2);
+ SDOperand CC;
+ // TODO: handle Cond == OR / AND / XOR
+ if (Cond.getOpcode() == ISD::SETCC) {
+ CC = Cond.getOperand(2);
+ Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
+ Cond.getOperand(0), Cond.getOperand(1));
+ } else {
+ CC = DAG.getCondCode(ISD::SETNE);
+ Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
+ }
+ return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
+ Op.getOperand(0), Op.getOperand(2), CC, Cond);
+ }
}
}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.3 llvm/lib/Target/X86/X86ISelLowering.h:1.4
--- llvm/lib/Target/X86/X86ISelLowering.h:1.3 Fri Dec 16 19:21:05 2005
+++ llvm/lib/Target/X86/X86ISelLowering.h Mon Dec 19 17:12:38 2005
@@ -72,6 +72,9 @@
/// X86 conditional moves.
CMOV,
+
+ /// X86 conditional branches.
+ BRCOND,
};
}
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.172 llvm/lib/Target/X86/X86InstrInfo.td:1.173
--- llvm/lib/Target/X86/X86InstrInfo.td:1.172 Sat Dec 17 13:47:05 2005
+++ llvm/lib/Target/X86/X86InstrInfo.td Mon Dec 19 17:12:38 2005
@@ -24,10 +24,15 @@
[SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
SDTCisVT<3, OtherVT>, SDTCisVT<4, FlagVT>]>;
-def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, []>;
-def X86test : SDNode<"X86ISD::TEST", SDTX86CmpTest, []>;
+def SDTX86BrCond : SDTypeProfile<0, 3,
+ [SDTCisVT<0, OtherVT>,
+ SDTCisVT<1, OtherVT>, SDTCisVT<2, FlagVT>]>;
-def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov, []>;
+def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, []>;
+def X86test : SDNode<"X86ISD::TEST", SDTX86CmpTest, []>;
+
+def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov, []>;
+def X86Brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, [SDNPHasChain]>;
//===----------------------------------------------------------------------===//
// X86 Operand Definitions.
@@ -268,21 +273,33 @@
let isBarrier = 1 in
def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
+
+def JE : IBr<0x84, (ops brtarget:$dst), "je $dst",
+ [(X86Brcond bb:$dst, SETEQ, STATUS)]>, Imp<[STATUS],[]>, TB;
+def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst",
+ [(X86Brcond bb:$dst, SETNE, STATUS)]>, Imp<[STATUS],[]>, TB;
+def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst",
+ [(X86Brcond bb:$dst, SETLT, STATUS)]>, Imp<[STATUS],[]>, TB;
+def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst",
+ [(X86Brcond bb:$dst, SETLE, STATUS)]>, Imp<[STATUS],[]>, TB;
+def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst",
+ [(X86Brcond bb:$dst, SETGT, STATUS)]>, Imp<[STATUS],[]>, TB;
+def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst",
+ [(X86Brcond bb:$dst, SETGE, STATUS)]>, Imp<[STATUS],[]>, TB;
+
def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst",
- []>, TB;
-def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst", []>, TB;
-def JE : IBr<0x84, (ops brtarget:$dst), "je $dst", []>, TB;
-def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst", []>, TB;
-def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst", []>, TB;
-def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst", []>, TB;
+ [(X86Brcond bb:$dst, SETULT, STATUS)]>, Imp<[STATUS],[]>, TB;
+def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst",
+ [(X86Brcond bb:$dst, SETULE, STATUS)]>, Imp<[STATUS],[]>, TB;
+def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst",
+ [(X86Brcond bb:$dst, SETUGT, STATUS)]>, Imp<[STATUS],[]>, TB;
+def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst",
+ [(X86Brcond bb:$dst, SETUGE, STATUS)]>, Imp<[STATUS],[]>, TB;
+
def JS : IBr<0x88, (ops brtarget:$dst), "js $dst", []>, TB;
def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst", []>, TB;
def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst", []>, TB;
def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst", []>, TB;
-def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst", []>, TB;
-def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst", []>, TB;
-def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst", []>, TB;
-def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst", []>, TB;
//===----------------------------------------------------------------------===//
// Call Instructions...
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