[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
Jim Laskey
jlaskey at apple.com
Mon Dec 19 08:30:24 PST 2005
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.51 -> 1.52
---
Log message:
Create a strong dependency for loads following stores. This will leave a
latency period between the two.
---
Diffs of the changes: (+6 -2)
ScheduleDAG.cpp | 8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.51 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.52
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.51 Sun Dec 18 16:20:05 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Mon Dec 19 10:30:13 2005
@@ -281,7 +281,9 @@
InstrStage *StageBegin; // First stage in itinerary
InstrStage *StageEnd; // Last+1 stage in itinerary
unsigned Latency; // Total cycles to complete instruction
- bool IsCall; // Is function call
+ bool IsCall : 1; // Is function call
+ bool IsLoad : 1; // Is memory load
+ bool IsStore : 1; // Is memory store
unsigned Slot; // Node's time slot
NodeGroup *Group; // Grouping information
unsigned VRBase; // Virtual register base
@@ -756,6 +758,8 @@
// Get machine opcode
MachineOpCode TOpc = Node->getTargetOpcode();
NI->IsCall = TII.isCall(TOpc);
+ NI->IsLoad = TII.isLoad(TOpc);
+ NI->IsStore = TII.isStore(TOpc);
if (TII.isLoad(TOpc)) NI->StageBegin = &LoadStage;
else if (TII.isStore(TOpc)) NI->StageBegin = &StoreStage;
@@ -857,7 +861,7 @@
/// I.E., B must wait for latency of A.
bool SimpleSched::isStrongDependency(NodeInfo *A, NodeInfo *B) {
// If A defines for B then it's a strong dependency
- return isDefiner(A, B);
+ return isDefiner(A, B) || (A->IsStore && B->IsLoad);
}
/// isWeakDependency Return true if node A produces a result that will
More information about the llvm-commits
mailing list