[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp SparcV8InstrInfo.td SparcV8RegisterInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/SparcV8:

SparcV8ISelSimple.cpp updated: 1.93 -> 1.94
SparcV8InstrInfo.td updated: 1.65 -> 1.66
SparcV8RegisterInfo.td updated: 1.23 -> 1.24
---
Log message:

Add patterns for multiply, simplify Y register handling stuff, add RDY instruction


---
Diffs of the changes:  (+17 -17)

 SparcV8ISelSimple.cpp  |    4 ++--
 SparcV8InstrInfo.td    |   23 +++++++++++++++--------
 SparcV8RegisterInfo.td |    7 -------
 3 files changed, 17 insertions(+), 17 deletions(-)


Index: llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp:1.93 llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp:1.94
--- llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp:1.93	Sat Dec 17 14:18:48 2005
+++ llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp	Sat Dec 17 16:22:53 2005
@@ -1480,11 +1480,11 @@
       unsigned Tmp = makeAnotherReg (I.getType ());
       // Sign extend into the Y register
       BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
-      BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
+      BuildMI (BB, V8::WRYrr, 2).addReg (Tmp).addReg (V8::G0);
       BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
     } else {
       // Zero extend into the Y register, ie, just set it to zero
-      BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
+      BuildMI (BB, V8::WRYrr, 2).addReg (V8::G0).addReg (V8::G0);
       BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
     }
 


Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
diff -u llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.65 llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.66
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.65	Sat Dec 17 15:25:27 2005
+++ llvm/lib/Target/SparcV8/SparcV8InstrInfo.td	Sat Dec 17 16:22:53 2005
@@ -358,10 +358,12 @@
                    "umul $b, $c, $dst", []>;
 def SMULrr  : F3_1<2, 0b001011, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "smul $b, $c, $dst", []>;
+                   "smul $b, $c, $dst",
+                   [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
 def SMULri  : F3_2<2, 0b001011,
                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
-                   "smul $b, $c, $dst", []>;
+                   "smul $b, $c, $dst",
+                   [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
 
 // Section B.19 - Divide Instructions, p. 115
 def UDIVrr   : F3_1<2, 0b001110, 
@@ -467,13 +469,18 @@
                     "jmpl $b+$c, $dst", []>;
 }
 
+// Section B.28 - Read State Register Instructions
+def RDY : F3_1<2, 0b101000,
+               (ops IntRegs:$dst),
+               "rdy $dst", []>;
+
 // Section B.29 - Write State Register Instructions
-def WRrr : F3_1<2, 0b110000,
-                (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                "wr $b, $c, $dst", []>;
-def WRri : F3_2<2, 0b110000,
-                (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
-                "wr $b, $c, $dst", []>;
+def WRYrr : F3_1<2, 0b110000,
+                 (ops IntRegs:$b, IntRegs:$c),
+                 "wr $b, $c, %y", []>;
+def WRYri : F3_2<2, 0b110000,
+                 (ops IntRegs:$b, i32imm:$c),
+                 "wr $b, $c, %y", []>;
 
 // Convert Integer to Floating-point Instructions, p. 141
 def FITOS : F3_3<2, 0b110100, 0b011000100,


Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
diff -u llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.23 llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.24
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.23	Wed Nov 30 22:51:06 2005
+++ llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td	Sat Dec 17 16:22:53 2005
@@ -30,11 +30,6 @@
   let Num = num;
   let Aliases = aliases;
 }
-// Rs - Special "ancillary state registers" registers, like the Y, ASR, PSR,
-// WIM, TBR, etc registers
-class Rs<bits<5> num, string n> : SparcReg<n> {
-  let Num = num;
-}
 
 // Integer registers
 def G0 : Ri< 0, "G0">; def G1 : Ri< 1, "G1">; def G2 : Ri< 2, "G2">; 
@@ -76,8 +71,6 @@
 def D12 : Rd<24, "F24", [F24, F25]>; def D13 : Rd<26, "F26", [F26, F27]>; 
 def D14 : Rd<28, "F28", [F28, F29]>; def D15 : Rd<30, "F30", [F30, F31]>;
 
-// The Y register.
-def Y   : Rs<0, "Y">;
 
 // Register classes.
 //