[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td PPCRegisterInfo.td

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPCInstrInfo.td updated: 1.159 -> 1.160
PPCRegisterInfo.td updated: 1.26 -> 1.27
---
Log message:

Add a second vector type to the VRRC register class, and fix some patterns
so that tablegen can infer all types.


---
Diffs of the changes:  (+6 -6)

 PPCInstrInfo.td    |    6 +++---
 PPCRegisterInfo.td |    6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.159 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.160
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.159	Wed Dec 14 16:54:33 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Fri Dec 16 03:19:13 2005
@@ -946,11 +946,11 @@
               (srl GPRC:$rS, (sub 32, GPRC:$rB))),
           (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
 
-def : Pat<(zext GPRC:$in),
+def : Pat<(i64 (zext GPRC:$in)),
           (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
-def : Pat<(anyext GPRC:$in),
+def : Pat<(i64 (anyext GPRC:$in)),
           (OR4To8 GPRC:$in, GPRC:$in)>;
-def : Pat<(trunc G8RC:$in),
+def : Pat<(i32 (trunc G8RC:$in)),
           (OR8To4 G8RC:$in, G8RC:$in)>;
 
 // SHL


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.26 llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.27
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.26	Wed Nov 30 22:51:06 2005
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td	Fri Dec 16 03:19:13 2005
@@ -191,9 +191,9 @@
   F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
-def VRRC : RegisterClass<"PPC", [v4f32], 128, [V0, V1, V2, V3, V4, V5, V6, V7, 
-  V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23,
-  V24, V25, V26, V27, V28, V29, V30, V31]>;
+def VRRC : RegisterClass<"PPC", [v4f32,v4i32], 128, [V0, V1, V2, V3, V4, V5,
+  V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
+  V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>;
 
 def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, 
   CR3, CR4]>;