[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8InstrFormats.td SparcV8InstrInfo.td
Chris Lattner
lattner at cs.uiuc.edu
Thu Dec 15 22:25:53 PST 2005
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrFormats.td updated: 1.3 -> 1.4
SparcV8InstrInfo.td updated: 1.40 -> 1.41
---
Log message:
Add operand info for F3_[12] instructions, getting V8 back to basic functionality.
With this, Regression/CodeGen/SparcV8/basictest.ll now passes. Lets hear it
for regression tests :)
---
Diffs of the changes: (+198 -98)
SparcV8InstrFormats.td | 8 +
SparcV8InstrInfo.td | 288 ++++++++++++++++++++++++++++++++-----------------
2 files changed, 198 insertions(+), 98 deletions(-)
Index: llvm/lib/Target/SparcV8/SparcV8InstrFormats.td
diff -u llvm/lib/Target/SparcV8/SparcV8InstrFormats.td:1.3 llvm/lib/Target/SparcV8/SparcV8InstrFormats.td:1.4
--- llvm/lib/Target/SparcV8/SparcV8InstrFormats.td:1.3 Thu Oct 14 17:32:24 2004
+++ llvm/lib/Target/SparcV8/SparcV8InstrFormats.td Fri Dec 16 00:25:42 2005
@@ -58,10 +58,12 @@
// Specific F3 classes: SparcV8 manual, page 44
//
-class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3 {
+class F3_1<bits<2> opVal, bits<6> op3val, dag ops, string name> : F3 {
bits<8> asi = 0; // asi not currently used in SparcV8
bits<5> rs2;
+ dag OperandList = ops;
+
let op = opVal;
let op3 = op3val;
let Name = name;
@@ -71,9 +73,11 @@
let Inst{4-0} = rs2;
}
-class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3 {
+class F3_2<bits<2> opVal, bits<6> op3val, dag ops, string name> : F3 {
bits<13> simm13;
+ dag OperandList = ops;
+
let op = opVal;
let op3 = op3val;
let Name = name;
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
diff -u llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.40 llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.41
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.40 Fri Dec 16 00:02:58 2005
+++ llvm/lib/Target/SparcV8/SparcV8InstrInfo.td Fri Dec 16 00:25:42 2005
@@ -50,47 +50,74 @@
// special cases of JMPL:
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
- def RET : F3_2<2, 0b111000, "ret">;
+ def RET : F3_2<2, 0b111000,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ret">;
let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
- def RETL: F3_2<2, 0b111000, "retl">;
+ def RETL: F3_2<2, 0b111000,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "retl">;
}
// CMP is a special case of SUBCC where destination is ignored, by setting it to
// %g0 (hardwired zero).
// FIXME: should keep track of the fact that it defs the integer condition codes
let rd = 0 in
- def CMPri: F3_2<2, 0b010100, "cmp">;
+ def CMPri: F3_2<2, 0b010100,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "cmp">;
// Section B.1 - Load Integer Instructions, p. 90
-def LDSB: F3_2<3, 0b001001, "ldsb">;
-def LDSH: F3_2<3, 0b001010, "ldsh">;
-def LDUB: F3_2<3, 0b000001, "ldub">;
-def LDUH: F3_2<3, 0b000010, "lduh">;
-def LD : F3_2<3, 0b000000, "ld">;
-def LDD : F3_2<3, 0b000011, "ldd">;
+def LDSB: F3_2<3, 0b001001,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ldsb">;
+def LDSH: F3_2<3, 0b001010,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ldsh">;
+def LDUB: F3_2<3, 0b000001,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ldub">;
+def LDUH: F3_2<3, 0b000010,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "lduh">;
+def LD : F3_2<3, 0b000000,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ld">;
+def LDD : F3_2<3, 0b000011,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ldd">;
// Section B.2 - Load Floating-point Instructions, p. 92
-def LDFrr : F3_1<3, 0b100000, "ld">;
-def LDFri : F3_2<3, 0b100000, "ld">;
-def LDDFrr : F3_1<3, 0b100011, "ldd">;
-def LDDFri : F3_2<3, 0b100011, "ldd">;
-def LDFSRrr: F3_1<3, 0b100001, "ld">;
-def LDFSRri: F3_2<3, 0b100001, "ld">;
+def LDFrr : F3_1<3, 0b100000,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "ld">;
+def LDFri : F3_2<3, 0b100000,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ld">;
+def LDDFrr : F3_1<3, 0b100011,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "ldd">;
+def LDDFri : F3_2<3, 0b100011,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ldd">;
+def LDFSRrr: F3_1<3, 0b100001,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "ld">;
+def LDFSRri: F3_2<3, 0b100001,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "ld">;
// Section B.4 - Store Integer Instructions, p. 95
-def STB : F3_2<3, 0b000101, "stb">;
-def STH : F3_2<3, 0b000110, "sth">;
-def ST : F3_2<3, 0b000100, "st">;
-def STD : F3_2<3, 0b000111, "std">;
+def STB : F3_2<3, 0b000101,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "stb">;
+def STH : F3_2<3, 0b000110,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sth">;
+def ST : F3_2<3, 0b000100,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "st">;
+def STD : F3_2<3, 0b000111,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "std">;
// Section B.5 - Store Floating-point Instructions, p. 97
-def STFrr : F3_1<3, 0b100100, "st">;
-def STFri : F3_2<3, 0b100100, "st">;
-def STDFrr : F3_1<3, 0b100111, "std">;
-def STDFri : F3_2<3, 0b100111, "std">;
-def STFSRrr : F3_1<3, 0b100101, "st">;
-def STFSRri : F3_2<3, 0b100101, "st">;
-def STDFQrr : F3_1<3, 0b100110, "std">;
-def STDFQri : F3_2<3, 0b100110, "std">;
+def STFrr : F3_1<3, 0b100100,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "st">;
+def STFri : F3_2<3, 0b100100,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "st">;
+def STDFrr : F3_1<3, 0b100111,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "std">;
+def STDFri : F3_2<3, 0b100111,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "std">;
+def STFSRrr : F3_1<3, 0b100101,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "st">;
+def STFSRri : F3_2<3, 0b100101,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "st">;
+def STDFQrr : F3_1<3, 0b100110,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "std">;
+def STDFQri : F3_2<3, 0b100110,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "std">;
// Section B.9 - SETHI Instruction, p. 104
def SETHIi: F2_1<0b100, "sethi">;
@@ -101,84 +128,150 @@
def NOP : F2_1<0b100, "nop">;
// Section B.11 - Logical Instructions, p. 106
-def ANDrr : F3_1<2, 0b000001, "and">;
-def ANDri : F3_2<2, 0b000001, "and">;
-def ANDCCrr : F3_1<2, 0b010001, "andcc">;
-def ANDCCri : F3_2<2, 0b010001, "andcc">;
-def ANDNrr : F3_1<2, 0b000101, "andn">;
-def ANDNri : F3_2<2, 0b000101, "andn">;
-def ANDNCCrr: F3_1<2, 0b010101, "andncc">;
-def ANDNCCri: F3_2<2, 0b010101, "andncc">;
-def ORrr : F3_1<2, 0b000010, "or">;
-def ORri : F3_2<2, 0b000010, "or">;
-def ORCCrr : F3_1<2, 0b010010, "orcc">;
-def ORCCri : F3_2<2, 0b010010, "orcc">;
-def ORNrr : F3_1<2, 0b000110, "orn">;
-def ORNri : F3_2<2, 0b000110, "orn">;
-def ORNCCrr : F3_1<2, 0b010110, "orncc">;
-def ORNCCri : F3_2<2, 0b010110, "orncc">;
-def XORrr : F3_1<2, 0b000011, "xor">;
-def XORri : F3_2<2, 0b000011, "xor">;
-def XORCCrr : F3_1<2, 0b010011, "xorcc">;
-def XORCCri : F3_2<2, 0b010011, "xorcc">;
-def XNORrr : F3_1<2, 0b000111, "xnor">;
-def XNORri : F3_2<2, 0b000111, "xnor">;
-def XNORCCrr: F3_1<2, 0b010111, "xnorcc">;
-def XNORCCri: F3_2<2, 0b010111, "xnorcc">;
+def ANDrr : F3_1<2, 0b000001,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "and">;
+def ANDri : F3_2<2, 0b000001,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "and">;
+def ANDCCrr : F3_1<2, 0b010001,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "andcc">;
+def ANDCCri : F3_2<2, 0b010001,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "andcc">;
+def ANDNrr : F3_1<2, 0b000101,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "andn">;
+def ANDNri : F3_2<2, 0b000101,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "andn">;
+def ANDNCCrr: F3_1<2, 0b010101,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "andncc">;
+def ANDNCCri: F3_2<2, 0b010101,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "andncc">;
+def ORrr : F3_1<2, 0b000010,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "or">;
+def ORri : F3_2<2, 0b000010,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "or">;
+def ORCCrr : F3_1<2, 0b010010,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "orcc">;
+def ORCCri : F3_2<2, 0b010010,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "orcc">;
+def ORNrr : F3_1<2, 0b000110,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "orn">;
+def ORNri : F3_2<2, 0b000110,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "orn">;
+def ORNCCrr : F3_1<2, 0b010110,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "orncc">;
+def ORNCCri : F3_2<2, 0b010110,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "orncc">;
+def XORrr : F3_1<2, 0b000011,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "xor">;
+def XORri : F3_2<2, 0b000011,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "xor">;
+def XORCCrr : F3_1<2, 0b010011,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "xorcc">;
+def XORCCri : F3_2<2, 0b010011,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "xorcc">;
+def XNORrr : F3_1<2, 0b000111,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "xnor">;
+def XNORri : F3_2<2, 0b000111,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "xnor">;
+def XNORCCrr: F3_1<2, 0b010111,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "xnorcc">;
+def XNORCCri: F3_2<2, 0b010111,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "xnorcc">;
// Section B.12 - Shift Instructions, p. 107
-def SLLrr : F3_1<2, 0b100101, "sll">;
-def SLLri : F3_2<2, 0b100101, "sll">;
-def SRLrr : F3_1<2, 0b100110, "srl">;
-def SRLri : F3_2<2, 0b100110, "srl">;
-def SRArr : F3_1<2, 0b100111, "sra">;
-def SRAri : F3_2<2, 0b100111, "sra">;
+def SLLrr : F3_1<2, 0b100101,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "sll">;
+def SLLri : F3_2<2, 0b100101,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sll">;
+def SRLrr : F3_1<2, 0b100110,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "srl">;
+def SRLri : F3_2<2, 0b100110,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "srl">;
+def SRArr : F3_1<2, 0b100111,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "sra">;
+def SRAri : F3_2<2, 0b100111,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sra">;
// Section B.13 - Add Instructions, p. 108
-def ADDrr : F3_1<2, 0b000000, "add">;
-def ADDri : F3_2<2, 0b000000, "add">;
-def ADDCCrr : F3_1<2, 0b010000, "addcc">;
-def ADDCCri : F3_2<2, 0b010000, "addcc">;
-def ADDXrr : F3_1<2, 0b001000, "addx">;
-def ADDXri : F3_2<2, 0b001000, "addx">;
-def ADDXCCrr: F3_1<2, 0b011000, "addxcc">;
-def ADDXCCri: F3_2<2, 0b011000, "addxcc">;
+def ADDrr : F3_1<2, 0b000000,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "add">;
+def ADDri : F3_2<2, 0b000000,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "add">;
+def ADDCCrr : F3_1<2, 0b010000,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "addcc">;
+def ADDCCri : F3_2<2, 0b010000,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "addcc">;
+def ADDXrr : F3_1<2, 0b001000,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "addx">;
+def ADDXri : F3_2<2, 0b001000,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "addx">;
+def ADDXCCrr: F3_1<2, 0b011000,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "addxcc">;
+def ADDXCCri: F3_2<2, 0b011000,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "addxcc">;
// Section B.15 - Subtract Instructions, p. 110
-def SUBrr : F3_1<2, 0b000100, "sub">;
-def SUBri : F3_2<2, 0b000100, "sub">;
-def SUBCCrr : F3_1<2, 0b010100, "subcc">;
-def SUBCCri : F3_2<2, 0b010100, "subcc">;
-def SUBXrr : F3_1<2, 0b001100, "subx">;
-def SUBXri : F3_2<2, 0b001100, "subx">;
-def SUBXCCrr: F3_1<2, 0b011100, "subxcc">;
-def SUBXCCri: F3_2<2, 0b011100, "subxcc">;
+def SUBrr : F3_1<2, 0b000100,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "sub">;
+def SUBri : F3_2<2, 0b000100,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sub">;
+def SUBCCrr : F3_1<2, 0b010100,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "subcc">;
+def SUBCCri : F3_2<2, 0b010100,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "subcc">;
+def SUBXrr : F3_1<2, 0b001100,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "subx">;
+def SUBXri : F3_2<2, 0b001100,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "subx">;
+def SUBXCCrr: F3_1<2, 0b011100,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "subxcc">;
+def SUBXCCri: F3_2<2, 0b011100,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "subxcc">;
// Section B.18 - Multiply Instructions, p. 113
-def UMULrr : F3_1<2, 0b001010, "umul">;
-def UMULri : F3_2<2, 0b001010, "umul">;
-def SMULrr : F3_1<2, 0b001011, "smul">;
-def SMULri : F3_2<2, 0b001011, "smul">;
-def UMULCCrr: F3_1<2, 0b011010, "umulcc">;
-def UMULCCri: F3_2<2, 0b011010, "umulcc">;
-def SMULCCrr: F3_1<2, 0b011011, "smulcc">;
-def SMULCCri: F3_2<2, 0b011011, "smulcc">;
+def UMULrr : F3_1<2, 0b001010,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "umul">;
+def UMULri : F3_2<2, 0b001010,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "umul">;
+def SMULrr : F3_1<2, 0b001011,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "smul">;
+def SMULri : F3_2<2, 0b001011,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "smul">;
+def UMULCCrr: F3_1<2, 0b011010,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "umulcc">;
+def UMULCCri: F3_2<2, 0b011010,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "umulcc">;
+def SMULCCrr: F3_1<2, 0b011011,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "smulcc">;
+def SMULCCri: F3_2<2, 0b011011,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "smulcc">;
// Section B.19 - Divide Instructions, p. 115
-def UDIVrr : F3_1<2, 0b001110, "udiv">;
-def UDIVri : F3_2<2, 0b001110, "udiv">;
-def SDIVrr : F3_1<2, 0b001111, "sdiv">;
-def SDIVri : F3_2<2, 0b001111, "sdiv">;
-def UDIVCCrr : F3_1<2, 0b011110, "udivcc">;
-def UDIVCCri : F3_2<2, 0b011110, "udivcc">;
-def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">;
-def SDIVCCri : F3_2<2, 0b011111, "sdivcc">;
+def UDIVrr : F3_1<2, 0b001110,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "udiv">;
+def UDIVri : F3_2<2, 0b001110,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "udiv">;
+def SDIVrr : F3_1<2, 0b001111,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "sdiv">;
+def SDIVri : F3_2<2, 0b001111,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sdiv">;
+def UDIVCCrr : F3_1<2, 0b011110,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "udivcc">;
+def UDIVCCri : F3_2<2, 0b011110,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "udivcc">;
+def SDIVCCrr : F3_1<2, 0b011111,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "sdivcc">;
+def SDIVCCri : F3_2<2, 0b011111,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "sdivcc">;
// Section B.20 - SAVE and RESTORE, p. 117
-def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
-def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r
-def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r
-def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r
+def SAVErr : F3_1<2, 0b111100,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "save">;
+def SAVEri : F3_2<2, 0b111100,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "save">;
+def RESTORErr : F3_1<2, 0b111101,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "restore">;
+def RESTOREri : F3_2<2, 0b111101,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "restore">;
// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
@@ -248,12 +341,15 @@
// be an implicit def):
let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
- def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
+ def JMPLrr : F3_1<2, 0b111000, (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "jmpl">;
+ // jmpl [rs1+rs2], rd
}
// Section B.29 - Write State Register Instructions
-def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd
-def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd
+def WRrr : F3_1<2, 0b110000,
+ (ops IntRegs:$a, IntRegs:$b, IntRegs:$c), "wr">;
+def WRri : F3_2<2, 0b110000,
+ (ops IntRegs:$a, IntRegs:$b, i32imm:$c), "wr">; // wr rs1, imm, rd
// Convert Integer to Floating-point Instructions, p. 141
def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">;
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