[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86ISelPattern.cpp updated: 1.186 -> 1.187
---
Log message:

Fix test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll and PR672: http://llvm.cs.uiuc.edu/PR672 .

This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc
turned on.  Given a clean nightly tester run, we should be able to turn it
on by default!


---
Diffs of the changes:  (+14 -0)

 X86ISelPattern.cpp |   14 ++++++++++++++
 1 files changed, 14 insertions(+)


Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.186 llvm/lib/Target/X86/X86ISelPattern.cpp:1.187
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.186	Sun Nov 20 15:41:10 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp	Sat Dec  3 01:15:55 2005
@@ -3067,6 +3067,20 @@
 
   // TODO: handle jmp [mem]
   if (!isDirect) {
+    // We do not want the register allocator to allocate CalleeReg to a callee 
+    // saved register, as these will be restored before the JMP.  To prevent
+    // this, emit explicit clobbers of callee saved regs here.  A better way to
+    // solve this would be to specify that the register constraints of TAILJMPr
+    // only allow registers that are not callee saved, but we currently can't
+    // express that.  This forces all four of these regs to be saved and 
+    // reloaded for all functions with an indirect tail call.
+    // TODO: Improve this!
+    BuildMI(BB, X86::IMPLICIT_DEF, 4)
+       .addReg(X86::ESI, MachineOperand::Def)
+       .addReg(X86::EDI, MachineOperand::Def)
+       .addReg(X86::EBX, MachineOperand::Def)
+       .addReg(X86::EBP, MachineOperand::Def);
+    
     BuildMI(BB, X86::TAILJMPr, 1).addReg(CalleeReg);
   } else if (GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Callee)){
     BuildMI(BB, X86::TAILJMPd, 1).addGlobalAddress(GASD->getGlobal(), true);