[llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp SparcV9RegisterInfo.td

[Nate Begeman]

Changes in directory llvm/lib/Target/SparcV9:

SparcV9RegisterInfo.cpp updated: 1.9 -> 1.10
SparcV9RegisterInfo.td updated: 1.5 -> 1.6
---
Log message:

Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


---
Diffs of the changes:  (+12 -6)

 SparcV9RegisterInfo.cpp |   16 +++++++++++-----
 SparcV9RegisterInfo.td  |    2 +-
 2 files changed, 12 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.9 llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.10
--- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.9	Sun Oct  2 01:23:51 2005
+++ llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp	Wed Nov 30 22:51:06 2005
@@ -27,6 +27,7 @@
 
 #include "SparcV9RegisterInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/ValueTypes.h"
 using namespace llvm;
 
 namespace llvm {
@@ -42,8 +43,9 @@
     SparcV9::g2, SparcV9::g3, SparcV9::g4, SparcV9::g5, SparcV9::g6,
     SparcV9::g7, SparcV9::o6
   };
+  const MVT::ValueType IRVTs[] = { MVT::i64, MVT::Other };
   struct IRClass : public TargetRegisterClass {
-    IRClass() : TargetRegisterClass(MVT::i64, 8, 8, IR, IR + 32) {}
+    IRClass() : TargetRegisterClass(IRVTs, 8, 8, IR, IR + 32) {}
   } IRInstance;
 
 
@@ -66,12 +68,13 @@
     SparcV9::f58, SparcV9::f59, SparcV9::f60, SparcV9::f61,
     SparcV9::f62, SparcV9::f63
   };
+  const MVT::ValueType FRVTs[] = { MVT::f32, MVT::Other };
   // FIXME: The size is correct for the first 32 registers. The
   // latter 32 do not all really exist; you can only access every other
   // one (32, 34, ...), and they must contain double-fp or quad-fp
   // values... see below about the aliasing problems.
   struct FRClass : public TargetRegisterClass {
-    FRClass() : TargetRegisterClass(MVT::f32, 4, 8, FR, FR + 64) {}
+    FRClass() : TargetRegisterClass(FRVTs, 4, 8, FR, FR + 64) {}
   } FRInstance;
 
 
@@ -79,8 +82,9 @@
   const unsigned ICCR[] = {
     SparcV9::xcc, SparcV9::icc, SparcV9::ccr
   };
+  const MVT::ValueType ICCRVTs[] = { MVT::i1, MVT::Other };
   struct ICCRClass : public TargetRegisterClass {
-    ICCRClass() : TargetRegisterClass(MVT::i1, 1, 8, ICCR, ICCR + 3) {}
+    ICCRClass() : TargetRegisterClass(ICCRVTs, 1, 8, ICCR, ICCR + 3) {}
   } ICCRInstance;
 
 
@@ -88,8 +92,9 @@
   const unsigned FCCR[] = {
     SparcV9::fcc0, SparcV9::fcc1, SparcV9::fcc2, SparcV9::fcc3
   };
+  const MVT::ValueType FCCRVTs[] = { MVT::i1, MVT::Other };
   struct FCCRClass : public TargetRegisterClass {
-    FCCRClass() : TargetRegisterClass(MVT::i1, 1, 8, FCCR, FCCR + 4) {}
+    FCCRClass() : TargetRegisterClass(FCCRVTs, 1, 8, FCCR, FCCR + 4) {}
   } FCCRInstance;
 
 
@@ -97,8 +102,9 @@
   const unsigned SR[] = {
     SparcV9::fsr
   };
+  const MVT::ValueType SRVTs[] = { MVT::i64, MVT::Other };
   struct SRClass : public TargetRegisterClass {
-    SRClass() : TargetRegisterClass(MVT::i64, 8, 8, SR, SR + 1) {}
+    SRClass() : TargetRegisterClass(SRVTs, 8, 8, SR, SR + 1) {}
   } SRInstance;
 
 


Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td
diff -u llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.5 llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.6
--- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.5	Fri Aug 19 13:51:57 2005
+++ llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td	Wed Nov 30 22:51:06 2005
@@ -43,7 +43,7 @@
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<"V9", i64, 64, [G0, G1, G2, G3, G4, G5, G6, G7,
+def IntRegs : RegisterClass<"V9", [i64], 64, [G0, G1, G2, G3, G4, G5, G6, G7,
                                      O0, O1, O2, O3, O4, O5, O6, O7,
                                      L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5, I6, I7]>;