[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.td

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPCRegisterInfo.td updated: 1.24 -> 1.25
---
Log message:

Cosmetic change, better reflects actual values


---
Diffs of the changes:  (+5 -6)

 PPCRegisterInfo.td |   11 +++++------
 1 files changed, 5 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.24 llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.25
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.24	Mon Nov 28 23:45:29 2005
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td	Wed Nov 30 22:48:26 2005
@@ -28,8 +28,8 @@
 }
 
 // SPR - One of the 32-bit special-purpose registers
-class SPR<bits<5> num, string n> : PPCReg<n> {
-  field bits<5> Num = num;
+class SPR<bits<10> num, string n> : PPCReg<n> {
+  field bits<10> Num = num;
 }
 
 // FPR - One of the 32 64-bit floating-point registers
@@ -126,12 +126,11 @@
 def CR6 : CR<6, "cr6">; def CR7 : CR<7, "cr7">;
 
 // Link register
-// FIXME: encode actual spr numbers here
-def LR  : SPR<2,   "lr">;
+def LR  : SPR<8, "lr">;
 // Count register
-def CTR : SPR<3, "ctr">;
+def CTR : SPR<9, "ctr">;
 // VRsave register
-def VRSAVE: SPR<4, "VRsave">;
+def VRSAVE: SPR<256, "VRsave">;
 
 /// Register classes
 // Allocate volatiles first