[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPCInstrFormats.td updated: 1.58 -> 1.59
PPCInstrInfo.td updated: 1.146 -> 1.147
---
Log message:

Represent the encoding of the SPR instructions as they actually are, so
that we can use the correct SPR numbers in the InstrInfo.td file.  This is
necessary to support VRsave.


---
Diffs of the changes:  (+18 -8)

 PPCInstrFormats.td |   12 ++++++++++--
 PPCInstrInfo.td    |   14 ++++++++------
 2 files changed, 18 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.58 llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.59
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.58	Tue Nov 29 02:04:45 2005
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td	Tue Nov 29 16:42:50 2005
@@ -361,7 +361,16 @@
   bits<10> SPR;
 
   let Inst{6-10}  = RT;
-  let Inst{11-20} = SPR;
+  let Inst{11}    = SPR{4};
+  let Inst{12}    = SPR{3};
+  let Inst{13}    = SPR{2};
+  let Inst{14}    = SPR{1};
+  let Inst{15}    = SPR{0};
+  let Inst{16}    = SPR{9};
+  let Inst{17}    = SPR{8};
+  let Inst{18}    = SPR{7};
+  let Inst{19}    = SPR{6};
+  let Inst{20}    = SPR{5};
   let Inst{21-30} = xo;
   let Inst{31}    = 0;
 }
@@ -411,7 +420,6 @@
   let Inst{31}    = 0;
 }
 
-
 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
                 InstrItinClass itin>
   : XFXForm_1<opcode, xo, OL, asmstr, itin>;


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.146 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.147
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.146	Tue Nov 29 02:04:45 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Tue Nov 29 16:42:50 2005
@@ -560,15 +560,17 @@
 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
 // which means the SPR value needs to be multiplied by a factor of 32.
-def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
-def MFLR  : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
+def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
+def MFLR  : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT",  SprMFSPR>;
 def MFCR  : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
                       "mtcrf $FXM, $rS", BrMCRX>;
-def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
-                        "mfcr $rT, $FXM", SprMFCR>;
-def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
-def MTLR  : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
+def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
+                       "mfcr $rT, $FXM", SprMFCR>;
+def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
+def MTLR  : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
+def MTSPR : XFXForm_7<31, 467, (ops GPRC:$rS, u16imm:$UIMM), "mtspr $UIMM, $rS",
+                      SprMTSPR>;
 
 // XS-Form instructions.  Just 'sradi'
 //