[llvm-commits] CVS: llvm/utils/TableGen/CodeGenInstruction.h CodeGenTarget.cpp InstrInfoEmitter.cpp
Chris Lattner
lattner at cs.uiuc.edu
Fri Nov 18 23:06:08 PST 2005
Changes in directory llvm/utils/TableGen:
CodeGenInstruction.h updated: 1.12 -> 1.13
CodeGenTarget.cpp updated: 1.41 -> 1.42
InstrInfoEmitter.cpp updated: 1.32 -> 1.33
---
Log message:
Teach tblgen about instruction operands that have multiple MachineInstr
operands, digging into them to find register values (used on X86). Patch
by Evan Cheng!
---
Diffs of the changes: (+29 -9)
CodeGenInstruction.h | 11 +++++++++--
CodeGenTarget.cpp | 5 ++++-
InstrInfoEmitter.cpp | 22 ++++++++++++++++------
3 files changed, 29 insertions(+), 9 deletions(-)
Index: llvm/utils/TableGen/CodeGenInstruction.h
diff -u llvm/utils/TableGen/CodeGenInstruction.h:1.12 llvm/utils/TableGen/CodeGenInstruction.h:1.13
--- llvm/utils/TableGen/CodeGenInstruction.h:1.12 Fri Aug 26 15:42:52 2005
+++ llvm/utils/TableGen/CodeGenInstruction.h Sat Nov 19 01:05:57 2005
@@ -21,6 +21,7 @@
namespace llvm {
class Record;
+ class DagInit;
struct CodeGenInstruction {
Record *TheDef; // The actual record defining this instruction.
@@ -59,10 +60,16 @@
unsigned MIOperandNo;
unsigned MINumOperands; // The number of operands.
+ /// MIOperandInfo - Default MI operand type. Note an operand may be made up
+ /// of multiple MI operands.
+ DagInit *MIOperandInfo;
+
OperandInfo(Record *R, MVT::ValueType T, const std::string &N,
- const std::string &PMN, unsigned MION, unsigned MINO)
+ const std::string &PMN, unsigned MION, unsigned MINO,
+ DagInit *MIOI)
+
: Rec(R), Ty(T), Name(N), PrinterMethodName(PMN), MIOperandNo(MION),
- MINumOperands(MINO) {}
+ MINumOperands(MINO), MIOperandInfo(MIOI) {}
};
/// OperandList - The list of declared operands, along with their declared
Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.41 llvm/utils/TableGen/CodeGenTarget.cpp:1.42
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.41 Fri Oct 28 17:49:02 2005
+++ llvm/utils/TableGen/CodeGenTarget.cpp Sat Nov 19 01:05:57 2005
@@ -267,12 +267,14 @@
MVT::ValueType Ty;
std::string PrintMethod = "printOperand";
unsigned NumOps = 1;
+ DagInit *MIOpInfo;
if (Rec->isSubClassOf("RegisterClass")) {
Ty = getValueType(Rec->getValueAsDef("RegType"));
} else if (Rec->isSubClassOf("Operand")) {
Ty = getValueType(Rec->getValueAsDef("Type"));
PrintMethod = Rec->getValueAsString("PrintMethod");
NumOps = Rec->getValueAsInt("NumMIOperands");
+ MIOpInfo = Rec->getValueAsDag("MIOperandInfo");
} else if (Rec->getName() == "variable_ops") {
hasVariableNumberOfOperands = true;
continue;
@@ -289,7 +291,8 @@
" has the same name as a previous operand!";
OperandList.push_back(OperandInfo(Rec, Ty, DI->getArgName(i),
- PrintMethod, MIOperandNo, NumOps));
+ PrintMethod, MIOperandNo, NumOps,
+ MIOpInfo));
MIOperandNo += NumOps;
}
}
Index: llvm/utils/TableGen/InstrInfoEmitter.cpp
diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.32 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.33
--- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.32 Tue Nov 1 14:07:00 2005
+++ llvm/utils/TableGen/InstrInfoEmitter.cpp Sat Nov 19 01:05:57 2005
@@ -62,13 +62,21 @@
return Result; // No info for variable operand instrs.
for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
- if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass"))
+ if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) {
Result.push_back(Inst.OperandList[i].Rec);
- else {
+ } else {
// This might be a multiple operand thing.
- // FIXME: Targets like X86 have registers in their multi-operand operands.
- for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j)
- Result.push_back(0);
+ // Targets like X86 have registers in their multi-operand operands.
+ DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
+ unsigned NumDefs = MIOI->getNumArgs();
+ for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
+ if (NumDefs <= j) {
+ Result.push_back(0);
+ } else {
+ DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j));
+ Result.push_back(Def ? Def->getDef() : 0);
+ }
+ }
}
}
return Result;
@@ -124,7 +132,9 @@
N = ++OperandListNum;
OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
- if (Record *RC = OperandInfo[i]) {
+ Record *RC = OperandInfo[i];
+ // FIXME: We only care about register operands for now.
+ if (RC && RC->isSubClassOf("RegisterClass")) {
OS << "{ &" << getQualifiedName(RC) << "RegClass }, ";
} else {
OS << "{ 0 }, ";
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