[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h SelectionDAGNodes.h

[Nate Begeman]

Changes in directory llvm/include/llvm/CodeGen:

SelectionDAG.h updated: 1.68 -> 1.69
SelectionDAGNodes.h updated: 1.75 -> 1.76
---
Log message:

Teach LLVM how to scalarize packed types.  Currently, this only works on
packed types with an element count of 1, although more generic support is
coming.  This allows LLVM to turn the following code:

void %foo(<1 x float> * %a) {
entry:
  %tmp1 = load <1 x float> * %a;
  %tmp2 = add <1 x float> %tmp1, %tmp1
  store <1 x float> %tmp2, <1 x float> *%a
  ret void
}

Into:

_foo:
        lfs f0, 0(r3)
        fadds f0, f0, f0
        stfs f0, 0(r3)
        blr


---
Diffs of the changes:  (+13 -1)

 SelectionDAG.h      |    2 ++
 SelectionDAGNodes.h |   12 +++++++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.68 llvm/include/llvm/CodeGen/SelectionDAG.h:1.69
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.68	Wed Nov  9 17:46:43 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.h	Fri Nov 18 18:36:38 2005
@@ -257,6 +257,8 @@
   ///
   SDOperand getLoad(MVT::ValueType VT, SDOperand Chain, SDOperand Ptr,
                     SDOperand SV);
+  SDOperand getVecLoad(unsigned Count, MVT::ValueType VT, SDOperand Chain, 
+                       SDOperand Ptr, SDOperand SV);
   SDOperand getExtLoad(unsigned Opcode, MVT::ValueType VT, SDOperand Chain,
                        SDOperand Ptr, SDOperand SV, MVT::ValueType EVT);
 


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.75 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.76
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.75	Fri Nov 11 16:48:54 2005
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Fri Nov 18 18:36:38 2005
@@ -107,12 +107,17 @@
     // big.  Like EXTRACT_ELEMENT, this can only be used before legalization.
     BUILD_PAIR,
 
-
     // Simple integer binary arithmetic operators.
     ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
     
     // Simple binary floating point operators.
     FADD, FSUB, FMUL, FDIV, FREM,
+    
+    // Simple abstract vector operators.  Unlike the integer and floating point
+    // binary operators, these nodes also take two additional operands:
+    // a constant element count, and a value type node indicating the type of
+    // the elements.  The order is count, type, op0, op1.
+    VADD, VSUB, VMUL,
 
     // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
     // an unsigned/signed value of type i[2*n], then return the top part.
@@ -209,6 +214,11 @@
     // operand, then the same operands as an LLVM load/store instruction, then a
     // SRCVALUE node that provides alias analysis information.
     LOAD, STORE,
+    
+    // Abstract vector version of LOAD.  VLOAD has a token chain as the first
+    // operand, followed by a pointer operand, a constant element count, a value
+    // type node indicating the type of the elements, and a SRCVALUE node.
+    VLOAD,
 
     // EXTLOAD, SEXTLOAD, ZEXTLOAD - These three operators all load a value from
     // memory and extend them to a larger value (e.g. load a byte into a word