[llvm-commits] [vector_llvm] CVS: llvm/lib/Target/Alpha/Alpha.h Alpha.td AlphaISelDAGToDAG.cpp AlphaISelLowering.cpp AlphaISelLowering.h AlphaISelPattern.cpp AlphaInstrFormats.td AlphaInstrInfo.cpp AlphaInstrInfo.td AlphaRegisterInfo.cpp AlphaRegisterInfo.h AlphaRegisterInfo.td AlphaSubtarget.cpp AlphaSubtarget.h AlphaTargetMachine.cpp AlphaTargetMachine.h Makefile
Robert Bocchino
bocchino at cs.uiuc.edu
Wed Nov 16 10:32:44 PST 2005
Changes in directory llvm/lib/Target/Alpha:
Alpha.h updated: 1.4 -> 1.4.2.1
Alpha.td updated: 1.4 -> 1.4.2.1
AlphaISelDAGToDAG.cpp added (r1.5.4.2)
AlphaISelLowering.cpp updated: 1.7 -> 1.7.2.1
AlphaISelLowering.h updated: 1.1 -> 1.1.2.1
AlphaISelPattern.cpp updated: 1.173 -> 1.173.2.1
AlphaInstrFormats.td updated: 1.6 -> 1.6.2.1
AlphaInstrInfo.cpp updated: 1.5 -> 1.5.4.1
AlphaInstrInfo.td updated: 1.59 -> 1.59.2.1
AlphaRegisterInfo.cpp updated: 1.28 -> 1.28.2.1
AlphaRegisterInfo.h updated: 1.7 -> 1.7.2.1
AlphaRegisterInfo.td updated: 1.12 -> 1.12.2.1
AlphaSubtarget.cpp updated: 1.3 -> 1.3.2.1
AlphaSubtarget.h updated: 1.1 -> 1.1.2.1
AlphaTargetMachine.cpp updated: 1.13 -> 1.13.2.1
AlphaTargetMachine.h updated: 1.10 -> 1.10.2.1
Makefile updated: 1.2 -> 1.2.4.1
---
Log message:
Merged mainline into Vector LLVM branch
---
Diffs of the changes: (+996 -530)
Alpha.h | 1
Alpha.td | 24 +
AlphaISelDAGToDAG.cpp | 288 ++++++++++++++++++++++
AlphaISelLowering.cpp | 4
AlphaISelLowering.h | 9
AlphaISelPattern.cpp | 253 +++++--------------
AlphaInstrFormats.td | 96 ++++---
AlphaInstrInfo.cpp | 4
AlphaInstrInfo.td | 632 +++++++++++++++++++++++++++++++------------------
AlphaRegisterInfo.cpp | 71 ++++-
AlphaRegisterInfo.h | 3
AlphaRegisterInfo.td | 55 +++-
AlphaSubtarget.cpp | 44 ---
AlphaSubtarget.h | 4
AlphaTargetMachine.cpp | 27 +-
AlphaTargetMachine.h | 8
Makefile | 3
17 files changed, 996 insertions(+), 530 deletions(-)
Index: llvm/lib/Target/Alpha/Alpha.h
diff -u llvm/lib/Target/Alpha/Alpha.h:1.4 llvm/lib/Target/Alpha/Alpha.h:1.4.2.1
--- llvm/lib/Target/Alpha/Alpha.h:1.4 Fri Jul 22 15:52:16 2005
+++ llvm/lib/Target/Alpha/Alpha.h Wed Nov 16 12:32:33 2005
@@ -24,6 +24,7 @@
class MachineCodeEmitter;
FunctionPass *createAlphaSimpleInstructionSelector(TargetMachine &TM);
+ FunctionPass *createAlphaISelDag(TargetMachine &TM);
FunctionPass *createAlphaCodePrinterPass(std::ostream &OS,
TargetMachine &TM);
FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
Index: llvm/lib/Target/Alpha/Alpha.td
diff -u llvm/lib/Target/Alpha/Alpha.td:1.4 llvm/lib/Target/Alpha/Alpha.td:1.4.2.1
--- llvm/lib/Target/Alpha/Alpha.td:1.4 Thu Jun 23 18:42:05 2005
+++ llvm/lib/Target/Alpha/Alpha.td Wed Nov 16 12:32:33 2005
@@ -17,6 +17,15 @@
//Alpha is little endian
//===----------------------------------------------------------------------===//
+// Subtarget Features
+//===----------------------------------------------------------------------===//
+
+def FeatureCIX : SubtargetFeature<"CIX", "bool", "HasCT",
+ "Enable CIX extentions">;
+def FeatureFIX : SubtargetFeature<"FIX", "bool", "HasF2I",
+ "Enable FIX extentions">;
+
+//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
@@ -36,6 +45,21 @@
// let TSFlagsShifts = [];
}
+//===----------------------------------------------------------------------===//
+// Alpha Processor Definitions
+//===----------------------------------------------------------------------===//
+
+def : Processor<"generic", NoItineraries, []>;
+def : Processor<"pca56" , NoItineraries, []>;
+def : Processor<"ev56" , NoItineraries, []>;
+def : Processor<"ev6" , NoItineraries, [FeatureFIX]>;
+def : Processor<"ev67" , NoItineraries, [FeatureFIX, FeatureCIX]>;
+
+//===----------------------------------------------------------------------===//
+// The Alpha Target
+//===----------------------------------------------------------------------===//
+
+
def Alpha : Target {
// Pointers on Alpha are 64-bits in size.
let PointerType = i64;
Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -c /dev/null llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.5.4.2
*** /dev/null Wed Nov 16 12:32:44 2005
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Wed Nov 16 12:32:33 2005
***************
*** 0 ****
--- 1,288 ----
+ //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Andrew Lenharth and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file defines a pattern matching instruction selector for Alpha,
+ // converting from a legalized dag to a Alpha dag.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #include "Alpha.h"
+ #include "AlphaTargetMachine.h"
+ #include "AlphaISelLowering.h"
+ #include "llvm/CodeGen/MachineInstrBuilder.h"
+ #include "llvm/CodeGen/MachineFunction.h"
+ #include "llvm/CodeGen/SSARegMap.h"
+ #include "llvm/CodeGen/SelectionDAG.h"
+ #include "llvm/CodeGen/SelectionDAGISel.h"
+ #include "llvm/Target/TargetOptions.h"
+ #include "llvm/ADT/Statistic.h"
+ #include "llvm/Constants.h"
+ #include "llvm/GlobalValue.h"
+ #include "llvm/Support/Debug.h"
+ #include "llvm/Support/MathExtras.h"
+ #include <algorithm>
+ using namespace llvm;
+
+ namespace {
+
+ //===--------------------------------------------------------------------===//
+ /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
+ /// instructions for SelectionDAG operations.
+ ///
+ class AlphaDAGToDAGISel : public SelectionDAGISel {
+ AlphaTargetLowering AlphaLowering;
+
+ public:
+ AlphaDAGToDAGISel(TargetMachine &TM)
+ : SelectionDAGISel(AlphaLowering), AlphaLowering(TM) {}
+
+ /// getI64Imm - Return a target constant with the specified value, of type
+ /// i64.
+ inline SDOperand getI64Imm(int64_t Imm) {
+ return CurDAG->getTargetConstant(Imm, MVT::i64);
+ }
+
+ // Select - Convert the specified operand from a target-independent to a
+ // target-specific node if it hasn't already been changed.
+ SDOperand Select(SDOperand Op);
+
+ /// InstructionSelectBasicBlock - This callback is invoked by
+ /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
+ virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
+
+ virtual const char *getPassName() const {
+ return "Alpha DAG->DAG Pattern Instruction Selection";
+ }
+
+ // Include the pieces autogenerated from the target description.
+ #include "AlphaGenDAGISel.inc"
+
+ private:
+ SDOperand getGlobalBaseReg();
+ SDOperand SelectCALL(SDOperand Op);
+
+ };
+ }
+
+ /// getGlobalBaseReg - Output the instructions required to put the
+ /// GOT address into a register.
+ ///
+ SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
+ return CurDAG->getRegister(AlphaLowering.getVRegGP(), MVT::i64);
+ }
+
+ /// InstructionSelectBasicBlock - This callback is invoked by
+ /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
+ void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
+ DEBUG(BB->dump());
+
+ // Select target instructions for the DAG.
+ DAG.setRoot(Select(DAG.getRoot()));
+ CodeGenMap.clear();
+ DAG.RemoveDeadNodes();
+
+ // Emit machine code to BB.
+ ScheduleAndEmitDAG(DAG);
+ }
+
+ // Select - Convert the specified operand from a target-independent to a
+ // target-specific node if it hasn't already been changed.
+ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
+ SDNode *N = Op.Val;
+ if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
+ N->getOpcode() < AlphaISD::FIRST_NUMBER)
+ return Op; // Already selected.
+
+ // If this has already been converted, use it.
+ std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
+ if (CGMI != CodeGenMap.end()) return CGMI->second;
+
+ switch (N->getOpcode()) {
+ default: break;
+ case ISD::TAILCALL:
+ case ISD::CALL: return SelectCALL(Op);
+
+ case ISD::DYNAMIC_STACKALLOC:
+ assert(0 && "You want these too?");
+
+ case ISD::BRCOND: {
+ SDOperand Chain = Select(N->getOperand(0));
+ SDOperand CC = Select(N->getOperand(1));
+ CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC, Chain);
+ return SDOperand(N, 0);
+ }
+ case ISD::LOAD:
+ case ISD::EXTLOAD:
+ case ISD::ZEXTLOAD:
+ case ISD::SEXTLOAD: {
+ SDOperand Chain = Select(N->getOperand(0));
+ SDOperand Address = Select(N->getOperand(1));
+ unsigned opcode = N->getOpcode();
+ unsigned Opc = Alpha::WTF;
+ if (opcode == ISD::LOAD)
+ switch (N->getValueType(0)) {
+ default: N->dump(); assert(0 && "Bad load!");
+ case MVT::i64: Opc = Alpha::LDQ; break;
+ case MVT::f64: Opc = Alpha::LDT; break;
+ case MVT::f32: Opc = Alpha::LDS; break;
+ }
+ else
+ switch (cast<VTSDNode>(N->getOperand(3))->getVT()) {
+ default: N->dump(); assert(0 && "Bad sign extend!");
+ case MVT::i32: Opc = Alpha::LDL;
+ assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
+ case MVT::i16: Opc = Alpha::LDWU;
+ assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
+ case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
+ case MVT::i8: Opc = Alpha::LDBU;
+ assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
+ }
+
+ CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
+ getI64Imm(0), Address, Chain);
+ return SDOperand(N, Op.ResNo);
+ }
+
+ case ISD::BR: {
+ CurDAG->SelectNodeTo(N, Alpha::BR_DAG, MVT::Other, N->getOperand(1),
+ Select(N->getOperand(0)));
+ return SDOperand(N, 0);
+ }
+
+ case ISD::UNDEF:
+ if (N->getValueType(0) == MVT::i64)
+ CurDAG->SelectNodeTo(N, Alpha::IDEF, MVT::i64);
+ // else if (N->getValueType(0) == MVT::f32)
+ // CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F4, MVT::f32);
+ // else
+ // CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F8, MVT::f64);
+ return SDOperand(N, 0);
+ case ISD::FrameIndex: {
+ // int FI = cast<FrameIndexSDNode>(N)->getIndex();
+ // CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
+ // CurDAG->getTargetFrameIndex(FI, MVT::i32),
+ // getI32Imm(0));
+ // return SDOperand(N, 0);
+ assert(0 && "Frame?, you are suppose to look through the window, not at the frame!");
+ }
+ case ISD::ConstantPool: {
+ // Constant *C = cast<ConstantPoolSDNode>(N)->get();
+ // SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i32);
+ // if (PICEnabled)
+ // Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI);
+ // else
+ // Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
+ // CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
+ // return SDOperand(N, 0);
+ assert(0 && "Constants are overrated");
+ }
+ case ISD::GlobalAddress: {
+ GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
+ SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
+ CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, GA, getGlobalBaseReg());
+ return SDOperand(N, 0);
+ }
+ case ISD::ExternalSymbol:
+ CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64,
+ CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(), MVT::i64),
+ CurDAG->getRegister(AlphaLowering.getVRegGP(), MVT::i64));
+ return SDOperand(N, 0);
+
+ case ISD::CALLSEQ_START:
+ case ISD::CALLSEQ_END: {
+ unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
+ unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
+ Alpha::ADJUSTSTACKDOWN : Alpha::ADJUSTSTACKUP;
+ CurDAG->SelectNodeTo(N, Opc, MVT::Other,
+ getI64Imm(Amt), Select(N->getOperand(0)));
+ return SDOperand(N, 0);
+ }
+ case ISD::RET: {
+ SDOperand Chain = Select(N->getOperand(0)); // Token chain.
+
+ if (N->getNumOperands() == 2) {
+ SDOperand Val = Select(N->getOperand(1));
+ if (N->getOperand(1).getValueType() == MVT::i64) {
+ Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val);
+ }
+ }
+ //BuildMI(BB, Alpha::RET, 2, Alpha::R31).addReg(Alpha::R26).addImm(1);
+
+ // FIXME: add restoring of the RA to R26 to the chain
+ // Finally, select this to a ret instruction.
+ CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain);
+ return SDOperand(N, 0);
+ }
+
+
+
+ }
+
+ return SelectCode(Op);
+ }
+
+ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
+ SDNode *N = Op.Val;
+ SDOperand Chain = Select(N->getOperand(0));
+ SDOperand Addr = Select(N->getOperand(1));
+
+ // unsigned CallOpcode;
+ std::vector<SDOperand> CallOperands;
+ std::vector<MVT::ValueType> TypeOperands;
+
+ //grab the arguments
+ for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
+ TypeOperands.push_back(N->getOperand(i).getValueType());
+ CallOperands.push_back(Select(N->getOperand(i)));
+ }
+ int count = N->getNumOperands() - 2;
+
+ static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
+ Alpha::R19, Alpha::R20, Alpha::R21};
+ static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
+ Alpha::F19, Alpha::F20, Alpha::F21};
+
+ for (int i = 0; i < std::min(6, count); ++i) {
+ if (MVT::isInteger(TypeOperands[i])) {
+ Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i]);
+ } else {
+ assert(0 && "No FP support yet");
+ }
+ }
+ assert(CallOperands.size() <= 6 && "Too big a call");
+
+ Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr);
+ // Finally, once everything is in registers to pass to the call, emit the
+ // call itself.
+ Chain = CurDAG->getTargetNode(Alpha::JSRDAG, MVT::Other, Chain );
+
+ std::vector<SDOperand> CallResults;
+
+ switch (N->getValueType(0)) {
+ default: assert(0 && "Unexpected ret value!");
+ case MVT::Other: break;
+ case MVT::i64:
+ Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64).getValue(1);
+ CallResults.push_back(Chain.getValue(0));
+ break;
+ }
+
+ CallResults.push_back(Chain);
+ for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
+ CodeGenMap[Op.getValue(i)] = CallResults[i];
+ return CallResults[Op.ResNo];
+ }
+
+
+ /// createAlphaISelDag - This pass converts a legalized DAG into a
+ /// Alpha-specific DAG, ready for instruction scheduling.
+ ///
+ FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
+ return new AlphaDAGToDAGISel(TM);
+ }
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.7 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.7.2.1
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.7 Thu Oct 6 11:54:29 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Wed Nov 16 12:32:33 2005
@@ -50,8 +50,8 @@
setSetCCResultContents(ZeroOrOneSetCCResult);
addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
- addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass);
- addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass);
+ addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
+ addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
Index: llvm/lib/Target/Alpha/AlphaISelLowering.h
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.h:1.1 llvm/lib/Target/Alpha/AlphaISelLowering.h:1.1.2.1
--- llvm/lib/Target/Alpha/AlphaISelLowering.h:1.1 Fri Sep 2 13:46:02 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.h Wed Nov 16 12:32:33 2005
@@ -21,6 +21,13 @@
namespace llvm {
+ namespace AlphaISD {
+ enum NodeType {
+ // Start the numbering where the builting ops and target ops leave off.
+ FIRST_NUMBER = ISD::BUILTIN_OP_END+Alpha::INSTRUCTION_LIST_END,
+ };
+ }
+
class AlphaTargetLowering : public TargetLowering {
int VarArgsOffset; // What is the offset to the first vaarg
int VarArgsBase; // What is the base FrameIndex
@@ -52,6 +59,8 @@
void restoreGP(MachineBasicBlock* BB);
void restoreRA(MachineBasicBlock* BB);
+ unsigned getVRegGP() { return GP; }
+ unsigned getVRegRA() { return RA; }
};
}
Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.173 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.173.2.1
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.173 Thu Oct 6 11:54:29 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Wed Nov 16 12:32:33 2005
@@ -82,6 +82,10 @@
AlphaLowering(TM)
{}
+ virtual const char *getPassName() const {
+ return "Alpha Pattern Instruction Selection";
+ }
+
/// InstructionSelectBasicBlock - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
@@ -235,152 +239,6 @@
}
-//Shamelessly adapted from PPC32
-// Structure used to return the necessary information to codegen an SDIV as
-// a multiply.
-struct ms {
- int64_t m; // magic number
- int64_t s; // shift amount
-};
-
-struct mu {
- uint64_t m; // magic number
- int64_t a; // add indicator
- int64_t s; // shift amount
-};
-
-/// magic - calculate the magic numbers required to codegen an integer sdiv as
-/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
-/// or -1.
-static struct ms magic(int64_t d) {
- int64_t p;
- uint64_t ad, anc, delta, q1, r1, q2, r2, t;
- const uint64_t two63 = 9223372036854775808ULL; // 2^63
- struct ms mag;
-
- ad = llabs(d);
- t = two63 + ((uint64_t)d >> 63);
- anc = t - 1 - t%ad; // absolute value of nc
- p = 63; // initialize p
- q1 = two63/anc; // initialize q1 = 2p/abs(nc)
- r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
- q2 = two63/ad; // initialize q2 = 2p/abs(d)
- r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
- do {
- p = p + 1;
- q1 = 2*q1; // update q1 = 2p/abs(nc)
- r1 = 2*r1; // update r1 = rem(2p/abs(nc))
- if (r1 >= anc) { // must be unsigned comparison
- q1 = q1 + 1;
- r1 = r1 - anc;
- }
- q2 = 2*q2; // update q2 = 2p/abs(d)
- r2 = 2*r2; // update r2 = rem(2p/abs(d))
- if (r2 >= ad) { // must be unsigned comparison
- q2 = q2 + 1;
- r2 = r2 - ad;
- }
- delta = ad - r2;
- } while (q1 < delta || (q1 == delta && r1 == 0));
-
- mag.m = q2 + 1;
- if (d < 0) mag.m = -mag.m; // resulting magic number
- mag.s = p - 64; // resulting shift
- return mag;
-}
-
-/// magicu - calculate the magic numbers required to codegen an integer udiv as
-/// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
-static struct mu magicu(uint64_t d)
-{
- int64_t p;
- uint64_t nc, delta, q1, r1, q2, r2;
- struct mu magu;
- magu.a = 0; // initialize "add" indicator
- nc = - 1 - (-d)%d;
- p = 63; // initialize p
- q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
- r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
- q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
- r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
- do {
- p = p + 1;
- if (r1 >= nc - r1 ) {
- q1 = 2*q1 + 1; // update q1
- r1 = 2*r1 - nc; // update r1
- }
- else {
- q1 = 2*q1; // update q1
- r1 = 2*r1; // update r1
- }
- if (r2 + 1 >= d - r2) {
- if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
- q2 = 2*q2 + 1; // update q2
- r2 = 2*r2 + 1 - d; // update r2
- }
- else {
- if (q2 >= 0x8000000000000000ull) magu.a = 1;
- q2 = 2*q2; // update q2
- r2 = 2*r2 + 1; // update r2
- }
- delta = d - 1 - r2;
- } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
- magu.m = q2 + 1; // resulting magic number
- magu.s = p - 64; // resulting shift
- return magu;
-}
-
-/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
-/// return a DAG expression to select that will generate the same value by
-/// multiplying by a magic number. See:
-/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
-SDOperand AlphaISel::BuildSDIVSequence(SDOperand N) {
- int64_t d = (int64_t)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
- ms magics = magic(d);
- // Multiply the numerator (operand 0) by the magic value
- SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i64, N.getOperand(0),
- ISelDAG->getConstant(magics.m, MVT::i64));
- // If d > 0 and m < 0, add the numerator
- if (d > 0 && magics.m < 0)
- Q = ISelDAG->getNode(ISD::ADD, MVT::i64, Q, N.getOperand(0));
- // If d < 0 and m > 0, subtract the numerator.
- if (d < 0 && magics.m > 0)
- Q = ISelDAG->getNode(ISD::SUB, MVT::i64, Q, N.getOperand(0));
- // Shift right algebraic if shift value is nonzero
- if (magics.s > 0)
- Q = ISelDAG->getNode(ISD::SRA, MVT::i64, Q,
- ISelDAG->getConstant(magics.s, MVT::i64));
- // Extract the sign bit and add it to the quotient
- SDOperand T =
- ISelDAG->getNode(ISD::SRL, MVT::i64, Q, ISelDAG->getConstant(63, MVT::i64));
- return ISelDAG->getNode(ISD::ADD, MVT::i64, Q, T);
-}
-
-/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
-/// return a DAG expression to select that will generate the same value by
-/// multiplying by a magic number. See:
-/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
-SDOperand AlphaISel::BuildUDIVSequence(SDOperand N) {
- unsigned d =
- (unsigned)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
- mu magics = magicu(d);
- // Multiply the numerator (operand 0) by the magic value
- SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i64, N.getOperand(0),
- ISelDAG->getConstant(magics.m, MVT::i64));
- if (magics.a == 0) {
- Q = ISelDAG->getNode(ISD::SRL, MVT::i64, Q,
- ISelDAG->getConstant(magics.s, MVT::i64));
- } else {
- SDOperand NPQ = ISelDAG->getNode(ISD::SUB, MVT::i64, N.getOperand(0), Q);
- NPQ = ISelDAG->getNode(ISD::SRL, MVT::i64, NPQ,
- ISelDAG->getConstant(1, MVT::i64));
- NPQ = ISelDAG->getNode(ISD::ADD, MVT::i64, NPQ, Q);
- Q = ISelDAG->getNode(ISD::SRL, MVT::i64, NPQ,
- ISelDAG->getConstant(magics.s-1, MVT::i64));
- }
- return Q;
-}
-
//These describe LDAx
static const int IMM_LOW = -32768;
static const int IMM_HIGH = 32767;
@@ -511,7 +369,7 @@
//assert(0 && "Setcc On float?\n");
std::cerr << "Setcc on float!\n";
Tmp3 = MakeReg(MVT::f64);
- BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Alpha::F31).addReg(Tmp1);
+ BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp1);
Tmp1 = Tmp3;
}
if (SetCC->getOperand(1).getValueType() == MVT::f32)
@@ -519,7 +377,7 @@
//assert (0 && "Setcc On float?\n");
std::cerr << "Setcc on float!\n";
Tmp3 = MakeReg(MVT::f64);
- BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Alpha::F31).addReg(Tmp2);
+ BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp2);
Tmp2 = Tmp3;
}
@@ -652,7 +510,7 @@
unsigned Tmp1, Tmp2 = 0, Tmp3;
unsigned Opc = 0;
unsigned opcode = N.getOpcode();
- int64_t SImm;
+ int64_t SImm = 0;
uint64_t UImm;
SDNode *Node = N.Val;
@@ -691,13 +549,23 @@
Node->dump();
assert(0 && "Node not handled!\n");
+ case ISD::READCYCLECOUNTER:
+ Select(N.getOperand(0)); //Select chain
+ if (Result != notIn)
+ ExprMap[N.getValue(1)] = notIn; // Generate the token
+ else
+ Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
+
+ BuildMI(BB, Alpha::RPCC, 1, Result).addReg(Alpha::R31);
+ return Result;
+
case ISD::CTPOP:
case ISD::CTTZ:
case ISD::CTLZ:
Opc = opcode == ISD::CTPOP ? Alpha::CTPOP :
(opcode == ISD::CTTZ ? Alpha::CTTZ : Alpha::CTLZ);
Tmp1 = SelectExpr(N.getOperand(0));
- BuildMI(BB, Opc, 1, Result).addReg(Alpha::R31).addReg(Tmp1);
+ BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
return Result;
case ISD::MULHU:
@@ -928,8 +796,11 @@
.addReg(argvregs[i]);
break;
case MVT::f32:
+ BuildMI(BB, Alpha::CPYSS, 2, args_float[i]).addReg(argvregs[i])
+ .addReg(argvregs[i]);
+ break;
case MVT::f64:
- BuildMI(BB, Alpha::CPYS, 2, args_float[i]).addReg(argvregs[i])
+ BuildMI(BB, Alpha::CPYST, 2, args_float[i]).addReg(argvregs[i])
.addReg(argvregs[i]);
break;
}
@@ -985,8 +856,10 @@
BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
break;
case MVT::f32:
- case MVT::f64:
- BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
+ BuildMI(BB, Alpha::CPYSS, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
+ break;
+ case MVT::f64:
+ BuildMI(BB, Alpha::CPYST, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
break;
}
return Result+N.ResNo;
@@ -1084,10 +957,10 @@
break;
}
case MVT::i16:
- BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Alpha::R31).addReg(Tmp1);
+ BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Tmp1);
break;
case MVT::i8:
- BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Alpha::R31).addReg(Tmp1);
+ BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1);
break;
case MVT::i1:
Tmp2 = MakeReg(MVT::i64);
@@ -1181,10 +1054,17 @@
Select(Chain);
unsigned r = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
//std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
- if (MVT::isFloatingPoint(N.getValue(0).getValueType()))
- BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
- else
+ switch(N.getValue(0).getValueType()) {
+ case MVT::f32:
+ BuildMI(BB, Alpha::CPYSS, 2, Result).addReg(r).addReg(r);
+ break;
+ case MVT::f64:
+ BuildMI(BB, Alpha::CPYST, 2, Result).addReg(r).addReg(r);
+ break;
+ default:
BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);
+ break;
+ }
return Result;
}
@@ -1390,20 +1270,7 @@
}
}
//Else fall through
-
case ISD::UDIV:
- {
- if (isSIntImmediate(N.getOperand(1), SImm) && (SImm >= 2 || SImm <= -2))
- {
- // If this is a divide by constant, we can emit code using some magic
- // constants to implement it as a multiply instead.
- ExprMap.erase(N);
- if (opcode == ISD::SDIV)
- return SelectExpr(BuildSDIVSequence(N));
- else
- return SelectExpr(BuildUDIVSequence(N));
- }
- }
//else fall though
case ISD::UREM:
case ISD::SREM: {
@@ -1438,11 +1305,11 @@
if (SrcType == MVT::f32)
{
Tmp2 = MakeReg(MVT::f64);
- BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1);
+ BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1);
Tmp1 = Tmp2;
}
Tmp2 = MakeReg(MVT::f64);
- BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1);
+ BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1);
MoveFP2Int(Tmp2, Result, true);
return Result;
@@ -1643,16 +1510,19 @@
if(ISD::FABS == N.getOperand(0).getOpcode())
{
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
- BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
+ BuildMI(BB, DestType == MVT::f64 ? Alpha::CPYSNT : Alpha::CPYSNS,
+ 2, Result).addReg(Alpha::F31).addReg(Tmp1);
} else {
Tmp1 = SelectExpr(N.getOperand(0));
- BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1);
+ BuildMI(BB, DestType == MVT::f64 ? Alpha::CPYSNT : Alpha::CPYSNS
+ , 2, Result).addReg(Tmp1).addReg(Tmp1);
}
return Result;
case ISD::FABS:
Tmp1 = SelectExpr(N.getOperand(0));
- BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
+ BuildMI(BB, DestType == MVT::f64 ? Alpha::CPYST : Alpha::CPYSS, 2, Result)
+ .addReg(Alpha::F31).addReg(Tmp1);
return Result;
case ISD::FP_ROUND:
@@ -1660,7 +1530,7 @@
N.getOperand(0).getValueType() == MVT::f64 &&
"only f64 to f32 conversion supported here");
Tmp1 = SelectExpr(N.getOperand(0));
- BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Alpha::F31).addReg(Tmp1);
+ BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Tmp1);
return Result;
case ISD::FP_EXTEND:
@@ -1668,16 +1538,18 @@
N.getOperand(0).getValueType() == MVT::f32 &&
"only f32 to f64 conversion supported here");
Tmp1 = SelectExpr(N.getOperand(0));
- BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Alpha::F31).addReg(Tmp1);
+ BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
return Result;
case ISD::ConstantFP:
if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
if (CN->isExactlyValue(+0.0)) {
- BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31)
+ BuildMI(BB, DestType == MVT::f64 ? Alpha::CPYST : Alpha::CPYSS
+ , 2, Result).addReg(Alpha::F31)
.addReg(Alpha::F31);
} else if ( CN->isExactlyValue(-0.0)) {
- BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31)
+ BuildMI(BB, DestType == MVT::f64 ? Alpha::CPYSNT : Alpha::CPYSNS,
+ 2, Result).addReg(Alpha::F31)
.addReg(Alpha::F31);
} else {
abort();
@@ -1693,7 +1565,7 @@
Tmp2 = MakeReg(MVT::f64);
MoveInt2FP(Tmp1, Tmp2, true);
Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
- BuildMI(BB, Opc, 1, Result).addReg(Alpha::F31).addReg(Tmp2);
+ BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
return Result;
}
@@ -1760,11 +1632,17 @@
Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
if (Tmp1 != Tmp2) {
- if (N.getOperand(2).getValueType() == MVT::f64 ||
- N.getOperand(2).getValueType() == MVT::f32)
- BuildMI(BB, Alpha::CPYS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
- else
+ switch(N.getOperand(2).getValueType()) {
+ case MVT::f64:
+ BuildMI(BB, Alpha::CPYST, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
+ break;
+ case MVT::f32:
+ BuildMI(BB, Alpha::CPYSS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
+ break;
+ default:
BuildMI(BB, Alpha::BIS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
+ break;
+ }
}
return;
@@ -1784,8 +1662,10 @@
default: Node->dump();
assert(0 && "All other types should have been promoted!!");
case MVT::f64:
+ BuildMI(BB, Alpha::CPYST, 2, Alpha::F0).addReg(Tmp1).addReg(Tmp1);
+ break;
case MVT::f32:
- BuildMI(BB, Alpha::CPYS, 2, Alpha::F0).addReg(Tmp1).addReg(Tmp1);
+ BuildMI(BB, Alpha::CPYSS, 2, Alpha::F0).addReg(Tmp1).addReg(Tmp1);
break;
case MVT::i32:
case MVT::i64:
@@ -1869,6 +1749,7 @@
case ISD::CopyFromReg:
case ISD::TAILCALL:
case ISD::CALL:
+ case ISD::READCYCLECOUNTER:
case ISD::DYNAMIC_STACKALLOC:
ExprMap.erase(N);
SelectExpr(N);
Index: llvm/lib/Target/Alpha/AlphaInstrFormats.td
diff -u llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.6 llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.6.2.1
--- llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.6 Thu Jul 28 13:14:47 2005
+++ llvm/lib/Target/Alpha/AlphaInstrFormats.td Wed Nov 16 12:32:33 2005
@@ -17,26 +17,28 @@
//Floating-point
//PALcode
-def u8imm : Operand<i8>;
-def s14imm : Operand<i16>;
-def s16imm : Operand<i16>;
-def s21imm : Operand<i32>;
+def u8imm : Operand<i64>;
+def s14imm : Operand<i64>;
+def s16imm : Operand<i64>;
+def s21imm : Operand<i64>;
def s64imm : Operand<i64>;
//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//
-
-class InstAlpha<bits<6> op, dag OL, string asmstr> : Instruction { // Alpha instruction baseline
+// Alpha instruction baseline
+class InstAlphaAlt<bits<6> op, string asmstr> : Instruction {
field bits<32> Inst;
let Namespace = "Alpha";
- let OperandList = OL;
let AsmString = asmstr;
-
-
let Inst{31-26} = op;
}
+class InstAlpha<bits<6> op, dag OL, string asmstr>
+: InstAlphaAlt<op, asmstr> { // Alpha instruction baseline
+ let OperandList = OL;
+}
+
//3.3.1
class MForm<bits<6> opcode, string asmstr>
: InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), asmstr> {
@@ -48,6 +50,15 @@
let Inst{20-16} = Rb;
let Inst{15-0} = disp;
}
+class MfcForm<bits<6> opcode, bits<16> fc, string asmstr>
+ : InstAlpha<opcode, (ops GPRC:$RA, GPRC:$RB), asmstr> {
+ bits<5> Ra;
+ bits<5> Rb;
+
+ let Inst{25-21} = Ra;
+ let Inst{20-16} = Rb;
+ let Inst{15-0} = fc;
+}
class MgForm<bits<6> opcode, string asmstr>
: InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM), asmstr> {
@@ -81,10 +92,18 @@
let Inst{25-21} = Ra;
let Inst{20-0} = disp;
}
+class BFormD<bits<6> opcode, string asmstr>
+ : InstAlpha<opcode, (ops s21imm:$DISP), asmstr> {
+ bits<5> Ra = 31;
+ bits<21> disp;
+
+ let Inst{25-21} = Ra;
+ let Inst{20-0} = disp;
+}
let isBranch = 1, isTerminator = 1 in
class FBForm<bits<6> opcode, string asmstr>
- : InstAlpha<opcode, (ops FPRC:$RA, s21imm:$DISP), asmstr> {
+ : InstAlpha<opcode, (ops F8RC:$RA, s21imm:$DISP), asmstr> {
bits<5> Ra;
bits<21> disp;
@@ -93,8 +112,10 @@
}
//3.3.3
-class OForm<bits<6> opcode, bits<7> fun, string asmstr>
+class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
: InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), asmstr> {
+ let Pattern = pattern;
+
bits<5> Rc;
bits<5> Ra;
bits<5> Rb;
@@ -108,13 +129,30 @@
let Inst{4-0} = Rc;
}
-class OcmForm<bits<6> opcode, bits<7> fun, dag OL, string asmstr>
- : InstAlpha<opcode, OL, asmstr> {
- bits<5> Ra;
+class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
+ : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RB), asmstr> {
+ let Pattern = pattern;
+
+ bits<5> Rc;
bits<5> Rb;
bits<7> Function = fun;
+
+ let Inst{25-21} = 31;
+ let Inst{20-16} = Rb;
+ let Inst{15-13} = 0;
+ let Inst{12} = 0;
+ let Inst{11-5} = Function;
+ let Inst{4-0} = Rc;
+}
+
+class OForm4<bits<6> opcode, bits<7> fun, string asmstr>
+ : InstAlpha<opcode, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), asmstr> {
bits<5> Rc;
+ bits<5> Rb;
+ bits<5> Ra;
+ bits<7> Function = fun;
+ let isTwoAddress = 1;
let Inst{25-21} = Ra;
let Inst{20-16} = Rb;
let Inst{15-13} = 0;
@@ -124,8 +162,10 @@
}
-class OFormL<bits<6> opcode, bits<7> fun, string asmstr>
+class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
: InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), asmstr> {
+ let Pattern = pattern;
+
bits<5> Rc;
bits<5> Ra;
bits<8> LIT;
@@ -138,13 +178,14 @@
let Inst{4-0} = Rc;
}
-class OcmFormL<bits<6> opcode, bits<7> fun, dag OL, string asmstr>
- : InstAlpha<opcode, OL, asmstr> {
- bits<5> Ra;
+class OForm4L<bits<6> opcode, bits<7> fun, string asmstr>
+ : InstAlpha<opcode, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), asmstr> {
+ bits<5> Rc;
bits<8> LIT;
+ bits<5> Ra;
bits<7> Function = fun;
- bits<5> Rc;
+ let isTwoAddress = 1;
let Inst{25-21} = Ra;
let Inst{20-13} = LIT;
let Inst{12} = 1;
@@ -153,21 +194,10 @@
}
//3.3.4
-class FPForm<bits<6> opcode, bits<11> fun, string asmstr>
- : InstAlpha<opcode, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), asmstr> {
- bits<5> Fc;
- bits<5> Fa;
- bits<5> Fb;
- bits<11> Function = fun;
-
- let Inst{25-21} = Fa;
- let Inst{20-16} = Fb;
- let Inst{15-5} = Function;
- let Inst{4-0} = Fc;
-}
+class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern>
+ : InstAlphaAlt<opcode, asmstr> {
+ let Pattern = pattern;
-class FPFormCM<bits<6> opcode, bits<11> fun, dag OL, string asmstr>
- : InstAlpha<opcode, OL, asmstr> {
bits<5> Fc;
bits<5> Fa;
bits<5> Fb;
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.cpp:1.5 llvm/lib/Target/Alpha/AlphaInstrInfo.cpp:1.5.4.1
--- llvm/lib/Target/Alpha/AlphaInstrInfo.cpp:1.5 Thu Apr 21 18:10:23 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.cpp Wed Nov 16 12:32:33 2005
@@ -26,7 +26,9 @@
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
- if (oc == Alpha::BIS || oc == Alpha::CPYS) { // or r1, r2, r2 // cpys r1 r2 r2
+ if (oc == Alpha::BIS || oc == Alpha::CPYSS || oc == Alpha::CPYST) {
+ // or r1, r2, r2
+ // cpys(s|t) r1 r2 r2
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.59 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.59.2.1
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.59 Thu Oct 6 11:53:32 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Wed Nov 16 12:32:33 2005
@@ -12,6 +12,62 @@
include "AlphaInstrFormats.td"
+//********************
+//Paterns for matching
+//********************
+
+def immUExt8 : PatLeaf<(imm), [{
+ // immUExt8 predicate - True if the immediate fits in a 8-bit zero extended
+ // field. Used by instructions like 'addi'.
+ return (unsigned long)N->getValue() == (unsigned char)N->getValue();
+}]>;
+def immSExt16 : PatLeaf<(imm), [{
+ // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
+ // field. Used by instructions like 'lda'.
+ return (int)N->getValue() == (short)N->getValue();
+}]>;
+
+def iZAPX : SDNodeXForm<imm, [{
+ // Transformation function: get the imm to ZAPi
+ uint64_t UImm = (uint64_t)N->getValue();
+ unsigned int build = 0;
+ for(int i = 0; i < 8; ++i)
+ {
+ if ((UImm & 0x00FF) == 0x00FF)
+ build |= 1 << i;
+ else if ((UImm & 0x00FF) != 0)
+ { build = 0; break; }
+ UImm >>= 8;
+ }
+ return getI64Imm(build);
+}]>;
+def immZAP : PatLeaf<(imm), [{
+ // immZAP predicate - True if the immediate fits is suitable for use in a
+ // ZAP instruction
+ uint64_t UImm = (uint64_t)N->getValue();
+ unsigned int build = 0;
+ for(int i = 0; i < 8; ++i)
+ {
+ if ((UImm & 0x00FF) == 0x00FF)
+ build |= 1 << i;
+ else if ((UImm & 0x00FF) != 0)
+ { build = 0; break; }
+ UImm >>= 8;
+ }
+ return build != 0;
+}], iZAPX>;
+
+
+def intop : PatFrag<(ops node:$op), (sext_inreg node:$op, i32)>;
+def add4 : PatFrag<(ops node:$op1, node:$op2),
+ (add (shl node:$op1, 2), node:$op2)>;
+def sub4 : PatFrag<(ops node:$op1, node:$op2),
+ (sub (shl node:$op1, 2), node:$op2)>;
+def add8 : PatFrag<(ops node:$op1, node:$op2),
+ (add (shl node:$op1, 3), node:$op2)>;
+def sub8 : PatFrag<(ops node:$op1, node:$op2),
+ (sub (shl node:$op1, 3), node:$op2)>;
+
// //#define FP $15
// //#define RA $26
// //#define PV $27
@@ -40,19 +96,19 @@
//really the ISel should emit multiple MBB
let isTwoAddress = 1 in {
//Conditional move of an int based on a FP CC
- def CMOVEQ_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, FPRC:$RCOND),
+ def CMOVEQ_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
"fbne $RCOND, 42f\n\tbis $RSRC_T,$RSRC_T,$RDEST\n42:\n">;
- def CMOVEQi_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, u8imm:$L, FPRC:$RCOND),
+ def CMOVEQi_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, u8imm:$L, F8RC:$RCOND),
"fbne $RCOND, 42f\n\taddq $$31,$L,$RDEST\n42:\n">;
- def CMOVNE_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, FPRC:$RCOND),
+ def CMOVNE_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
"fbeq $RCOND, 42f\n\tbis $RSRC_T,$RSRC_T,$RDEST\n42:\n">;
- def CMOVNEi_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, u8imm:$L, FPRC:$RCOND),
+ def CMOVNEi_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, u8imm:$L, F8RC:$RCOND),
"fbeq $RCOND, 42f\n\taddq $$31,$L,$RDEST\n42:\n">;
//Conditional move of an FP based on a Int CC
- def FCMOVEQ_INT : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, FPRC:$RCOND),
+ def FCMOVEQ_INT : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
"bne $RCOND, 42f\n\tcpys $RSRC_T,$RSRC_T,$RDEST\n42:\n">;
- def FCMOVNE_INT : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, FPRC:$RCOND),
+ def FCMOVNE_INT : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
"beq $RCOND, 42f\n\tcpys $RSRC_T,$RSRC_T,$RDEST\n42:\n">;
}
@@ -62,200 +118,250 @@
//Operation Form:
-let isTwoAddress = 1 in {
//conditional moves, int
- def CMOVEQ : OcmForm< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
- "cmoveq $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND = zero
- def CMOVEQi : OcmFormL< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
- "cmoveq $RCOND,$L,$RDEST">; //CMOVE if RCOND = zero
- def CMOVGE : OcmForm< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
- "cmovge $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND >= zero
- def CMOVGEi : OcmFormL< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
- "cmovge $RCOND,$L,$RDEST">; //CMOVE if RCOND >= zero
- def CMOVGT : OcmForm< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
- "cmovgt $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND > zero
- def CMOVGTi : OcmFormL< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
- "cmovgt $RCOND,$L,$RDEST">; //CMOVE if RCOND > zero
- def CMOVLBC : OcmForm< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
- "cmovlbc $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit clear
- def CMOVLBCi : OcmFormL< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
- "cmovlbc $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit clear
- def CMOVLBS : OcmForm< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
- "cmovlbs $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit set
- def CMOVLBSi : OcmFormL< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
- "cmovlbs $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit set
- def CMOVLE : OcmForm< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
- "cmovle $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND <= zero
- def CMOVLEi : OcmFormL< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
- "cmovle $RCOND,$L,$RDEST">; //CMOVE if RCOND <= zero
- def CMOVLT : OcmForm< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
- "cmovlt $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND < zero
- def CMOVLTi : OcmFormL< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
- "cmovlt $RCOND,$L,$RDEST">; //CMOVE if RCOND < zero
- def CMOVNE : OcmForm< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
- "cmovne $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND != zero
- def CMOVNEi : OcmFormL< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
- "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero
+def CMOVEQ : OForm4< 0x11, 0x24, "cmoveq $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND = zero
+def CMOVEQi : OForm4L< 0x11, 0x24, "cmoveq $RCOND,$L,$RDEST">; //CMOVE if RCOND = zero
+def CMOVGE : OForm4< 0x11, 0x46, "cmovge $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND >= zero
+def CMOVGEi : OForm4L< 0x11, 0x46, "cmovge $RCOND,$L,$RDEST">; //CMOVE if RCOND >= zero
+def CMOVGT : OForm4< 0x11, 0x66, "cmovgt $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND > zero
+def CMOVGTi : OForm4L< 0x11, 0x66, "cmovgt $RCOND,$L,$RDEST">; //CMOVE if RCOND > zero
+def CMOVLBC : OForm4< 0x11, 0x16, "cmovlbc $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit clear
+def CMOVLBCi : OForm4L< 0x11, 0x16, "cmovlbc $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit clear
+def CMOVLBS : OForm4< 0x11, 0x14, "cmovlbs $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit set
+def CMOVLBSi : OForm4L< 0x11, 0x14, "cmovlbs $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit set
+def CMOVLE : OForm4< 0x11, 0x64, "cmovle $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND <= zero
+def CMOVLEi : OForm4L< 0x11, 0x64, "cmovle $RCOND,$L,$RDEST">; //CMOVE if RCOND <= zero
+def CMOVLT : OForm4< 0x11, 0x44, "cmovlt $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND < zero
+def CMOVLTi : OForm4L< 0x11, 0x44, "cmovlt $RCOND,$L,$RDEST">; //CMOVE if RCOND < zero
+def CMOVNE : OForm4< 0x11, 0x26, "cmovne $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND != zero
+def CMOVNEi : OForm4L< 0x11, 0x26, "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero
//conditional moves, fp
- def FCMOVEQ : FPFormCM<0x17, 0x02A, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
- "fcmoveq $RCOND,$RSRC,$RDEST">; //FCMOVE if = zero
- def FCMOVGE : FPFormCM<0x17, 0x02D, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
- "fcmovge $RCOND,$RSRC,$RDEST">; //FCMOVE if >= zero
- def FCMOVGT : FPFormCM<0x17, 0x02F, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
- "fcmovgt $RCOND,$RSRC,$RDEST">; //FCMOVE if > zero
- def FCMOVLE : FPFormCM<0x17, 0x02E, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
- "fcmovle $RCOND,$RSRC,$RDEST">; //FCMOVE if <= zero
- def FCMOVLT : FPFormCM<0x17, 0x02, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
- "fcmovlt $RCOND,$RSRC,$RDEST">; // FCMOVE if < zero
- def FCMOVNE : FPFormCM<0x17, 0x02B, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
- "fcmovne $RCOND,$RSRC,$RDEST">; //FCMOVE if != zero
+let OperandList = (ops F8RC:$RDEST, F8RC:$RSRC2, F8RC:$RSRC, F8RC:$RCOND),
+ isTwoAddress = 1 in {
+def FCMOVEQ : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if = zero
+def FCMOVGE : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if >= zero
+def FCMOVGT : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if > zero
+def FCMOVLE : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if <= zero
+def FCMOVLT : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RSRC,$RDEST",[]>; // FCMOVE if < zero
+def FCMOVNE : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if != zero
}
-def ADDL : OForm< 0x10, 0x00, "addl $RA,$RB,$RC">; //Add longword
-def ADDLi : OFormL<0x10, 0x00, "addl $RA,$L,$RC">; //Add longword
-def ADDQ : OForm< 0x10, 0x20, "addq $RA,$RB,$RC">; //Add quadword
-def ADDQi : OFormL<0x10, 0x20, "addq $RA,$L,$RC">; //Add quadword
-def AMASK : OForm< 0x11, 0x61, "AMASK $RA,$RB,$RC">; //Architecture mask
-def AMASKi : OFormL<0x11, 0x61, "AMASK $RA,$L,$RC">; //Architecture mask
-def AND : OForm< 0x11, 0x00, "and $RA,$RB,$RC">; //Logical product
-def ANDi : OFormL<0x11, 0x00, "and $RA,$L,$RC">; //Logical product
-def BIC : OForm< 0x11, 0x08, "bic $RA,$RB,$RC">; //Bit clear
-def BICi : OFormL<0x11, 0x08, "bic $RA,$L,$RC">; //Bit clear
-def BIS : OForm< 0x11, 0x20, "bis $RA,$RB,$RC">; //Logical sum
-def BISi : OFormL<0x11, 0x20, "bis $RA,$L,$RC">; //Logical sum
-def CTLZ : OForm< 0x1C, 0x32, "CTLZ $RB,$RC">; //Count leading zero
-def CTPOP : OForm< 0x1C, 0x30, "CTPOP $RB,$RC">; //Count population
-def CTTZ : OForm< 0x1C, 0x33, "CTTZ $RB,$RC">; //Count trailing zero
-def EQV : OForm< 0x11, 0x48, "eqv $RA,$RB,$RC">; //Logical equivalence
-def EQVi : OFormL<0x11, 0x48, "eqv $RA,$L,$RC">; //Logical equivalence
-def EXTBL : OForm< 0x12, 0x06, "EXTBL $RA,$RB,$RC">; //Extract byte low
-def EXTBLi : OFormL<0x12, 0x06, "EXTBL $RA,$L,$RC">; //Extract byte low
-def EXTLH : OForm< 0x12, 0x6A, "EXTLH $RA,$RB,$RC">; //Extract longword high
-def EXTLHi : OFormL<0x12, 0x6A, "EXTLH $RA,$L,$RC">; //Extract longword high
-def EXTLL : OForm< 0x12, 0x26, "EXTLL $RA,$RB,$RC">; //Extract longword low
-def EXTLLi : OFormL<0x12, 0x26, "EXTLL $RA,$L,$RC">; //Extract longword low
-def EXTQH : OForm< 0x12, 0x7A, "EXTQH $RA,$RB,$RC">; //Extract quadword high
-def EXTQHi : OFormL<0x12, 0x7A, "EXTQH $RA,$L,$RC">; //Extract quadword high
-def EXTQ : OForm< 0x12, 0x36, "EXTQ $RA,$RB,$RC">; //Extract quadword low
-def EXTQi : OFormL<0x12, 0x36, "EXTQ $RA,$L,$RC">; //Extract quadword low
-def EXTWH : OForm< 0x12, 0x5A, "EXTWH $RA,$RB,$RC">; //Extract word high
-def EXTWHi : OFormL<0x12, 0x5A, "EXTWH $RA,$L,$RC">; //Extract word high
-def EXTWL : OForm< 0x12, 0x16, "EXTWL $RA,$RB,$RC">; //Extract word low
-def EXTWLi : OFormL<0x12, 0x16, "EXTWL $RA,$L,$RC">; //Extract word low
-def IMPLVER : OForm< 0x11, 0x6C, "IMPLVER $RA,$RB,$RC">; //Implementation version
-def IMPLVERi : OFormL<0x11, 0x6C, "IMPLVER $RA,$L,$RC">; //Implementation version
-def INSBL : OForm< 0x12, 0x0B, "INSBL $RA,$RB,$RC">; //Insert byte low
-def INSBLi : OFormL<0x12, 0x0B, "INSBL $RA,$L,$RC">; //Insert byte low
-def INSLH : OForm< 0x12, 0x67, "INSLH $RA,$RB,$RC">; //Insert longword high
-def INSLHi : OFormL<0x12, 0x67, "INSLH $RA,$L,$RC">; //Insert longword high
-def INSLL : OForm< 0x12, 0x2B, "INSLL $RA,$RB,$RC">; //Insert longword low
-def INSLLi : OFormL<0x12, 0x2B, "INSLL $RA,$L,$RC">; //Insert longword low
-def INSQH : OForm< 0x12, 0x77, "INSQH $RA,$RB,$RC">; //Insert quadword high
-def INSQHi : OFormL<0x12, 0x77, "INSQH $RA,$L,$RC">; //Insert quadword high
-def INSQL : OForm< 0x12, 0x3B, "INSQL $RA,$RB,$RC">; //Insert quadword low
-def INSQLi : OFormL<0x12, 0x3B, "INSQL $RA,$L,$RC">; //Insert quadword low
-def INSWH : OForm< 0x12, 0x57, "INSWH $RA,$RB,$RC">; //Insert word high
-def INSWHi : OFormL<0x12, 0x57, "INSWH $RA,$L,$RC">; //Insert word high
-def INSWL : OForm< 0x12, 0x1B, "INSWL $RA,$RB,$RC">; //Insert word low
-def INSWLi : OFormL<0x12, 0x1B, "INSWL $RA,$L,$RC">; //Insert word low
-def MSKBL : OForm< 0x12, 0x02, "MSKBL $RA,$RB,$RC">; //Mask byte low
-def MSKBLi : OFormL<0x12, 0x02, "MSKBL $RA,$L,$RC">; //Mask byte low
-def MSKLH : OForm< 0x12, 0x62, "MSKLH $RA,$RB,$RC">; //Mask longword high
-def MSKLHi : OFormL<0x12, 0x62, "MSKLH $RA,$L,$RC">; //Mask longword high
-def MSKLL : OForm< 0x12, 0x22, "MSKLL $RA,$RB,$RC">; //Mask longword low
-def MSKLLi : OFormL<0x12, 0x22, "MSKLL $RA,$L,$RC">; //Mask longword low
-def MSKQH : OForm< 0x12, 0x72, "MSKQH $RA,$RB,$RC">; //Mask quadword high
-def MSKQHi : OFormL<0x12, 0x72, "MSKQH $RA,$L,$RC">; //Mask quadword high
-def MSKQL : OForm< 0x12, 0x32, "MSKQL $RA,$RB,$RC">; //Mask quadword low
-def MSKQLi : OFormL<0x12, 0x32, "MSKQL $RA,$L,$RC">; //Mask quadword low
-def MSKWH : OForm< 0x12, 0x52, "MSKWH $RA,$RB,$RC">; //Mask word high
-def MSKWHi : OFormL<0x12, 0x52, "MSKWH $RA,$L,$RC">; //Mask word high
-def MSKWL : OForm< 0x12, 0x12, "MSKWL $RA,$RB,$RC">; //Mask word low
-def MSKWLi : OFormL<0x12, 0x12, "MSKWL $RA,$L,$RC">; //Mask word low
-def MULL : OForm< 0x13, 0x00, "mull $RA,$RB,$RC">; //Multiply longword
-def MULLi : OFormL<0x13, 0x00, "mull $RA,$L,$RC">; //Multiply longword
-def MULQ : OForm< 0x13, 0x20, "mulq $RA,$RB,$RC">; //Multiply quadword
-def MULQi : OFormL<0x13, 0x20, "mulq $RA,$L,$RC">; //Multiply quadword
-def ORNOT : OForm< 0x11, 0x28, "ornot $RA,$RB,$RC">; //Logical sum with complement
-def ORNOTi : OFormL<0x11, 0x28, "ornot $RA,$L,$RC">; //Logical sum with complement
-def S4ADDL : OForm< 0x10, 0x02, "s4addl $RA,$RB,$RC">; //Scaled add longword by 4
-def S4ADDLi : OFormL<0x10, 0x02, "s4addl $RA,$L,$RC">; //Scaled add longword by 4
-def S4ADDQ : OForm< 0x10, 0x22, "s4addq $RA,$RB,$RC">; //Scaled add quadword by 4
-def S4ADDQi : OFormL<0x10, 0x22, "s4addq $RA,$L,$RC">; //Scaled add quadword by 4
-def S4SUBL : OForm< 0x10, 0x0B, "s4subl $RA,$RB,$RC">; //Scaled subtract longword by 4
-def S4SUBLi : OFormL<0x10, 0x0B, "s4subl $RA,$L,$RC">; //Scaled subtract longword by 4
-def S4SUBQ : OForm< 0x10, 0x2B, "s4subq $RA,$RB,$RC">; //Scaled subtract quadword by 4
-def S4SUBQi : OFormL<0x10, 0x2B, "s4subq $RA,$L,$RC">; //Scaled subtract quadword by 4
-def S8ADDL : OForm< 0x10, 0x12, "s8addl $RA,$RB,$RC">; //Scaled add longword by 8
-def S8ADDLi : OFormL<0x10, 0x12, "s8addl $RA,$L,$RC">; //Scaled add longword by 8
-def S8ADDQ : OForm< 0x10, 0x32, "s8addq $RA,$RB,$RC">; //Scaled add quadword by 8
-def S8ADDQi : OFormL<0x10, 0x32, "s8addq $RA,$L,$RC">; //Scaled add quadword by 8
-def S8SUBL : OForm< 0x10, 0x1B, "s8subl $RA,$RB,$RC">; //Scaled subtract longword by 8
-def S8SUBLi : OFormL<0x10, 0x1B, "s8subl $RA,$L,$RC">; //Scaled subtract longword by 8
-def S8SUBQ : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC">; //Scaled subtract quadword by 8
-def S8SUBQi : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC">; //Scaled subtract quadword by 8
-def SEXTB : OForm< 0x1C, 0x00, "sextb $RB,$RC">; //Sign extend byte
-def SEXTW : OForm< 0x1C, 0x01, "sextw $RB,$RC">; //Sign extend word
-def SL : OForm< 0x12, 0x39, "sll $RA,$RB,$RC">; //Shift left logical
-def SLi : OFormL<0x12, 0x39, "sll $RA,$L,$RC">; //Shift left logical
-def SRA : OForm< 0x12, 0x3C, "sra $RA,$RB,$RC">; //Shift right arithmetic
-def SRAi : OFormL<0x12, 0x3C, "sra $RA,$L,$RC">; //Shift right arithmetic
-def SRL : OForm< 0x12, 0x34, "srl $RA,$RB,$RC">; //Shift right logical
-
-def SRLi : OFormL<0x12, 0x34, "srl $RA,$L,$RC">; //Shift right logical
-def SUBL : OForm< 0x10, 0x09, "subl $RA,$RB,$RC">; //Subtract longword
-def SUBLi : OFormL<0x10, 0x09, "subl $RA,$L,$RC">; //Subtract longword
-def SUBQ : OForm< 0x10, 0x29, "subq $RA,$RB,$RC">; //Subtract quadword
-def SUBQi : OFormL<0x10, 0x29, "subq $RA,$L,$RC">; //Subtract quadword
-def UMULH : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC">; //Unsigned multiply quadword high
-def UMULHi : OFormL<0x13, 0x30, "umulh $RA,$L,$RC">; //Unsigned multiply quadword high
-def XOR : OForm< 0x11, 0x40, "xor $RA,$RB,$RC">; //Logical difference
-def XORi : OFormL<0x11, 0x40, "xor $RA,$L,$RC">; //Logical difference
-def ZAP : OForm< 0x12, 0x30, "zap $RA,$RB,$RC">; //Zero bytes
-def ZAPi : OFormL<0x12, 0x30, "zap $RA,$L,$RC">; //Zero bytes
-def ZAPNOT : OForm< 0x12, 0x31, "zapnot $RA,$RB,$RC">; //Zero bytes not
-def ZAPNOTi : OFormL<0x12, 0x31, "zapnot $RA,$L,$RC">; //Zero bytes not
+def ADDL : OForm< 0x10, 0x00, "addl $RA,$RB,$RC",
+ [(set GPRC:$RC, (intop (add GPRC:$RA, GPRC:$RB)))]>;
+def ADDLi : OFormL<0x10, 0x00, "addl $RA,$L,$RC",
+ [(set GPRC:$RC, (intop (add GPRC:$RA, immUExt8:$L)))]>;
+def ADDQ : OForm< 0x10, 0x20, "addq $RA,$RB,$RC",
+ [(set GPRC:$RC, (add GPRC:$RA, GPRC:$RB))]>;
+def ADDQi : OFormL<0x10, 0x20, "addq $RA,$L,$RC",
+ [(set GPRC:$RC, (add GPRC:$RA, immUExt8:$L))]>;
+def AND : OForm< 0x11, 0x00, "and $RA,$RB,$RC",
+ [(set GPRC:$RC, (and GPRC:$RA, GPRC:$RB))]>;
+def ANDi : OFormL<0x11, 0x00, "and $RA,$L,$RC",
+ [(set GPRC:$RC, (and GPRC:$RA, immUExt8:$L))]>;
+def BIC : OForm< 0x11, 0x08, "bic $RA,$RB,$RC",
+ [(set GPRC:$RC, (and GPRC:$RA, (not GPRC:$RB)))]>;
+def BICi : OFormL<0x11, 0x08, "bic $RA,$L,$RC", []>;
+// [(set GPRC:$RC, (and GPRC:$RA, (not immUExt8:$L)))]>; //FIXME?
+def BIS : OForm< 0x11, 0x20, "bis $RA,$RB,$RC",
+ [(set GPRC:$RC, (or GPRC:$RA, GPRC:$RB))]>;
+def BISi : OFormL<0x11, 0x20, "bis $RA,$L,$RC",
+ [(set GPRC:$RC, (or GPRC:$RA, immUExt8:$L))]>;
+def CTLZ : OForm2<0x1C, 0x32, "CTLZ $RB,$RC",
+ [(set GPRC:$RC, (ctlz GPRC:$RB))]>;
+def CTPOP : OForm2<0x1C, 0x30, "CTPOP $RB,$RC",
+ [(set GPRC:$RC, (ctpop GPRC:$RB))]>;
+def CTTZ : OForm2<0x1C, 0x33, "CTTZ $RB,$RC",
+ [(set GPRC:$RC, (cttz GPRC:$RB))]>;
+def EQV : OForm< 0x11, 0x48, "eqv $RA,$RB,$RC",
+ [(set GPRC:$RC, (xor GPRC:$RA, (not GPRC:$RB)))]>;
+def EQVi : OFormL<0x11, 0x48, "eqv $RA,$L,$RC", []>;
+// [(set GPRC:$RC, (xor GPRC:$RA, (not immUExt8:$L)))]>;
+//def EXTBL : OForm< 0x12, 0x06, "EXTBL $RA,$RB,$RC", []>; //Extract byte low
+//def EXTBLi : OFormL<0x12, 0x06, "EXTBL $RA,$L,$RC", []>; //Extract byte low
+//def EXTLH : OForm< 0x12, 0x6A, "EXTLH $RA,$RB,$RC", []>; //Extract longword high
+//def EXTLHi : OFormL<0x12, 0x6A, "EXTLH $RA,$L,$RC", []>; //Extract longword high
+//def EXTLL : OForm< 0x12, 0x26, "EXTLL $RA,$RB,$RC", []>; //Extract longword low
+//def EXTLLi : OFormL<0x12, 0x26, "EXTLL $RA,$L,$RC", []>; //Extract longword low
+//def EXTQH : OForm< 0x12, 0x7A, "EXTQH $RA,$RB,$RC", []>; //Extract quadword high
+//def EXTQHi : OFormL<0x12, 0x7A, "EXTQH $RA,$L,$RC", []>; //Extract quadword high
+//def EXTQ : OForm< 0x12, 0x36, "EXTQ $RA,$RB,$RC", []>; //Extract quadword low
+//def EXTQi : OFormL<0x12, 0x36, "EXTQ $RA,$L,$RC", []>; //Extract quadword low
+//def EXTWH : OForm< 0x12, 0x5A, "EXTWH $RA,$RB,$RC", []>; //Extract word high
+//def EXTWHi : OFormL<0x12, 0x5A, "EXTWH $RA,$L,$RC", []>; //Extract word high
+//def EXTWL : OForm< 0x12, 0x16, "EXTWL $RA,$RB,$RC", []>; //Extract word low
+//def EXTWLi : OFormL<0x12, 0x16, "EXTWL $RA,$L,$RC", []>; //Extract word low
+//def IMPLVER : OForm< 0x11, 0x6C, "IMPLVER $RA,$RB,$RC", []>; //Implementation version
+//def IMPLVERi : OFormL<0x11, 0x6C, "IMPLVER $RA,$L,$RC", []>; //Implementation version
+//def INSBL : OForm< 0x12, 0x0B, "INSBL $RA,$RB,$RC", []>; //Insert byte low
+//def INSBLi : OFormL<0x12, 0x0B, "INSBL $RA,$L,$RC", []>; //Insert byte low
+//def INSLH : OForm< 0x12, 0x67, "INSLH $RA,$RB,$RC", []>; //Insert longword high
+//def INSLHi : OFormL<0x12, 0x67, "INSLH $RA,$L,$RC", []>; //Insert longword high
+//def INSLL : OForm< 0x12, 0x2B, "INSLL $RA,$RB,$RC", []>; //Insert longword low
+//def INSLLi : OFormL<0x12, 0x2B, "INSLL $RA,$L,$RC", []>; //Insert longword low
+//def INSQH : OForm< 0x12, 0x77, "INSQH $RA,$RB,$RC", []>; //Insert quadword high
+//def INSQHi : OFormL<0x12, 0x77, "INSQH $RA,$L,$RC", []>; //Insert quadword high
+//def INSQL : OForm< 0x12, 0x3B, "INSQL $RA,$RB,$RC", []>; //Insert quadword low
+//def INSQLi : OFormL<0x12, 0x3B, "INSQL $RA,$L,$RC", []>; //Insert quadword low
+//def INSWH : OForm< 0x12, 0x57, "INSWH $RA,$RB,$RC", []>; //Insert word high
+//def INSWHi : OFormL<0x12, 0x57, "INSWH $RA,$L,$RC", []>; //Insert word high
+//def INSWL : OForm< 0x12, 0x1B, "INSWL $RA,$RB,$RC", []>; //Insert word low
+//def INSWLi : OFormL<0x12, 0x1B, "INSWL $RA,$L,$RC", []>; //Insert word low
+//def MSKBL : OForm< 0x12, 0x02, "MSKBL $RA,$RB,$RC", []>; //Mask byte low
+//def MSKBLi : OFormL<0x12, 0x02, "MSKBL $RA,$L,$RC", []>; //Mask byte low
+//def MSKLH : OForm< 0x12, 0x62, "MSKLH $RA,$RB,$RC", []>; //Mask longword high
+//def MSKLHi : OFormL<0x12, 0x62, "MSKLH $RA,$L,$RC", []>; //Mask longword high
+//def MSKLL : OForm< 0x12, 0x22, "MSKLL $RA,$RB,$RC", []>; //Mask longword low
+//def MSKLLi : OFormL<0x12, 0x22, "MSKLL $RA,$L,$RC", []>; //Mask longword low
+//def MSKQH : OForm< 0x12, 0x72, "MSKQH $RA,$RB,$RC", []>; //Mask quadword high
+//def MSKQHi : OFormL<0x12, 0x72, "MSKQH $RA,$L,$RC", []>; //Mask quadword high
+//def MSKQL : OForm< 0x12, 0x32, "MSKQL $RA,$RB,$RC", []>; //Mask quadword low
+//def MSKQLi : OFormL<0x12, 0x32, "MSKQL $RA,$L,$RC", []>; //Mask quadword low
+//def MSKWH : OForm< 0x12, 0x52, "MSKWH $RA,$RB,$RC", []>; //Mask word high
+//def MSKWHi : OFormL<0x12, 0x52, "MSKWH $RA,$L,$RC", []>; //Mask word high
+//def MSKWL : OForm< 0x12, 0x12, "MSKWL $RA,$RB,$RC", []>; //Mask word low
+//def MSKWLi : OFormL<0x12, 0x12, "MSKWL $RA,$L,$RC", []>; //Mask word low
+
+def MULL : OForm< 0x13, 0x00, "mull $RA,$RB,$RC",
+ [(set GPRC:$RC, (intop (mul GPRC:$RA, GPRC:$RB)))]>;
+def MULLi : OFormL<0x13, 0x00, "mull $RA,$L,$RC",
+ [(set GPRC:$RC, (intop (mul GPRC:$RA, immUExt8:$L)))]>;
+def MULQ : OForm< 0x13, 0x20, "mulq $RA,$RB,$RC",
+ [(set GPRC:$RC, (mul GPRC:$RA, GPRC:$RB))]>;
+def MULQi : OFormL<0x13, 0x20, "mulq $RA,$L,$RC",
+ [(set GPRC:$RC, (mul GPRC:$RA, immUExt8:$L))]>;
+def ORNOT : OForm< 0x11, 0x28, "ornot $RA,$RB,$RC",
+ [(set GPRC:$RC, (or GPRC:$RA, (not GPRC:$RB)))]>;
+def ORNOTi : OFormL<0x11, 0x28, "ornot $RA,$L,$RC", []>;
+// [(set GPRC:$RC, (or GPRC:$RA, (not immUExt8:$L)))]>;
+def S4ADDL : OForm< 0x10, 0x02, "s4addl $RA,$RB,$RC",
+ [(set GPRC:$RC, (intop (add4 GPRC:$RA, GPRC:$RB)))]>;
+def S4ADDLi : OFormL<0x10, 0x02, "s4addl $RA,$L,$RC",
+ [(set GPRC:$RC, (intop (add4 GPRC:$RA, immUExt8:$L)))]>;
+def S4ADDQ : OForm< 0x10, 0x22, "s4addq $RA,$RB,$RC",
+ [(set GPRC:$RC, (add4 GPRC:$RA, GPRC:$RB))]>;
+def S4ADDQi : OFormL<0x10, 0x22, "s4addq $RA,$L,$RC",
+ [(set GPRC:$RC, (add4 GPRC:$RA, immUExt8:$L))]>;
+def S4SUBL : OForm< 0x10, 0x0B, "s4subl $RA,$RB,$RC",
+ [(set GPRC:$RC, (intop (sub4 GPRC:$RA, GPRC:$RB)))]>;
+def S4SUBLi : OFormL<0x10, 0x0B, "s4subl $RA,$L,$RC",
+ [(set GPRC:$RC, (intop (sub4 GPRC:$RA, immUExt8:$L)))]>;
+def S4SUBQ : OForm< 0x10, 0x2B, "s4subq $RA,$RB,$RC",
+ [(set GPRC:$RC, (sub4 GPRC:$RA, GPRC:$RB))]>;
+def S4SUBQi : OFormL<0x10, 0x2B, "s4subq $RA,$L,$RC",
+ [(set GPRC:$RC, (sub4 GPRC:$RA, immUExt8:$L))]>;
+def S8ADDL : OForm< 0x10, 0x12, "s8addl $RA,$RB,$RC",
+ [(set GPRC:$RC, (intop (add8 GPRC:$RA, GPRC:$RB)))]>;
+def S8ADDLi : OFormL<0x10, 0x12, "s8addl $RA,$L,$RC",
+ [(set GPRC:$RC, (intop (add8 GPRC:$RA, immUExt8:$L)))]>;
+def S8ADDQ : OForm< 0x10, 0x32, "s8addq $RA,$RB,$RC",
+ [(set GPRC:$RC, (add8 GPRC:$RA, GPRC:$RB))]>;
+def S8ADDQi : OFormL<0x10, 0x32, "s8addq $RA,$L,$RC",
+ [(set GPRC:$RC, (add8 GPRC:$RA, immUExt8:$L))]>;
+def S8SUBL : OForm< 0x10, 0x1B, "s8subl $RA,$RB,$RC",
+ [(set GPRC:$RC, (intop (sub8 GPRC:$RA, GPRC:$RB)))]>;
+def S8SUBLi : OFormL<0x10, 0x1B, "s8subl $RA,$L,$RC",
+ [(set GPRC:$RC, (intop (sub8 GPRC:$RA, immUExt8:$L)))]>;
+def S8SUBQ : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC",
+ [(set GPRC:$RC, (sub8 GPRC:$RA, GPRC:$RB))]>;
+def S8SUBQi : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC",
+ [(set GPRC:$RC, (sub8 GPRC:$RA, immUExt8:$L))]>;
+def SEXTB : OForm2<0x1C, 0x00, "sextb $RB,$RC",
+ [(set GPRC:$RC, (sext_inreg GPRC:$RB, i8))]>;
+def SEXTW : OForm2<0x1C, 0x01, "sextw $RB,$RC",
+ [(set GPRC:$RC, (sext_inreg GPRC:$RB, i16))]>;
+def SL : OForm< 0x12, 0x39, "sll $RA,$RB,$RC",
+ [(set GPRC:$RC, (shl GPRC:$RA, GPRC:$RB))]>;
+def SLi : OFormL<0x12, 0x39, "sll $RA,$L,$RC",
+ [(set GPRC:$RC, (shl GPRC:$RA, immUExt8:$L))]>;
+def SRA : OForm< 0x12, 0x3C, "sra $RA,$RB,$RC",
+ [(set GPRC:$RC, (sra GPRC:$RA, GPRC:$RB))]>;
+def SRAi : OFormL<0x12, 0x3C, "sra $RA,$L,$RC",
+ [(set GPRC:$RC, (sra GPRC:$RA, immUExt8:$L))]>;
+def SRL : OForm< 0x12, 0x34, "srl $RA,$RB,$RC",
+ [(set GPRC:$RC, (srl GPRC:$RA, GPRC:$RB))]>;
+def SRLi : OFormL<0x12, 0x34, "srl $RA,$L,$RC",
+ [(set GPRC:$RC, (srl GPRC:$RA, immUExt8:$L))]>;
+def SUBL : OForm< 0x10, 0x09, "subl $RA,$RB,$RC",
+ [(set GPRC:$RC, (intop (sub GPRC:$RA, GPRC:$RB)))]>;
+def SUBLi : OFormL<0x10, 0x09, "subl $RA,$L,$RC",
+ [(set GPRC:$RC, (intop (sub GPRC:$RA, immUExt8:$L)))]>;
+def SUBQ : OForm< 0x10, 0x29, "subq $RA,$RB,$RC",
+ [(set GPRC:$RC, (sub GPRC:$RA, GPRC:$RB))]>;
+def SUBQi : OFormL<0x10, 0x29, "subq $RA,$L,$RC",
+ [(set GPRC:$RC, (sub GPRC:$RA, immUExt8:$L))]>;
+def UMULH : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC",
+ [(set GPRC:$RC, (mulhu GPRC:$RA, GPRC:$RB))]>;
+def UMULHi : OFormL<0x13, 0x30, "umulh $RA,$L,$RC",
+ [(set GPRC:$RC, (mulhu GPRC:$RA, immUExt8:$L))]>;
+def XOR : OForm< 0x11, 0x40, "xor $RA,$RB,$RC",
+ [(set GPRC:$RC, (xor GPRC:$RA, GPRC:$RB))]>;
+def XORi : OFormL<0x11, 0x40, "xor $RA,$L,$RC",
+ [(set GPRC:$RC, (xor GPRC:$RA, immUExt8:$L))]>;
+//FIXME: what to do about zap? the cases it catches are very complex
+def ZAP : OForm< 0x12, 0x30, "zap $RA,$RB,$RC", []>; //Zero bytes
+//ZAPi is useless give ZAPNOTi
+def ZAPi : OFormL<0x12, 0x30, "zap $RA,$L,$RC", []>; //Zero bytes
+//FIXME: what to do about zapnot? see ZAP :)
+def ZAPNOT : OForm< 0x12, 0x31, "zapnot $RA,$RB,$RC", []>; //Zero bytes not
+def ZAPNOTi : OFormL<0x12, 0x31, "zapnot $RA,$L,$RC",
+ [(set GPRC:$RC, (and GPRC:$RA, immZAP:$L))]>;
//Comparison, int
-def CMPBGE : OForm< 0x10, 0x0F, "cmpbge $RA,$RB,$RC">; //Compare byte
-def CMPBGEi : OFormL<0x10, 0x0F, "cmpbge $RA,$L,$RC">; //Compare byte
-def CMPEQ : OForm< 0x10, 0x2D, "cmpeq $RA,$RB,$RC">; //Compare signed quadword equal
-def CMPEQi : OFormL<0x10, 0x2D, "cmpeq $RA,$L,$RC">; //Compare signed quadword equal
-def CMPLE : OForm< 0x10, 0x6D, "cmple $RA,$RB,$RC">; //Compare signed quadword less than or equal
-def CMPLEi : OFormL<0x10, 0x6D, "cmple $RA,$L,$RC">; //Compare signed quadword less than or equal
-def CMPLT : OForm< 0x10, 0x4D, "cmplt $RA,$RB,$RC">; //Compare signed quadword less than
-def CMPLTi : OFormL<0x10, 0x4D, "cmplt $RA,$L,$RC">; //Compare signed quadword less than
-def CMPULE : OForm< 0x10, 0x3D, "cmpule $RA,$RB,$RC">; //Compare unsigned quadword less than or equal
-def CMPULEi : OFormL<0x10, 0x3D, "cmpule $RA,$L,$RC">; //Compare unsigned quadword less than or equal
-def CMPULT : OForm< 0x10, 0x1D, "cmpult $RA,$RB,$RC">; //Compare unsigned quadword less than
-def CMPULTi : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC">; //Compare unsigned quadword less than
-
-//Comparison, FP
-def CMPTEQ : FPForm<0x16, 0x0A5, "cmpteq/su $RA,$RB,$RC">; //Compare T_floating equal
-def CMPTLE : FPForm<0x16, 0x0A7, "cmptle/su $RA,$RB,$RC">; //Compare T_floating less than or equal
-def CMPTLT : FPForm<0x16, 0x0A6, "cmptlt/su $RA,$RB,$RC">; //Compare T_floating less than
-def CMPTUN : FPForm<0x16, 0x0A4, "cmptun/su $RA,$RB,$RC">; //Compare T_floating unordered
+//So this is a waste of what this instruction can do, but it still saves something
+def CMPBGE : OForm< 0x10, 0x0F, "cmpbge $RA,$RB,$RC",
+ [(set GPRC:$RC, (setuge (and GPRC:$RA, 255), (and GPRC:$RB, 255)))]>;
+def CMPBGEi : OFormL<0x10, 0x0F, "cmpbge $RA,$L,$RC",
+ [(set GPRC:$RC, (setuge (and GPRC:$RA, 255), immUExt8:$L))]>;
+def CMPEQ : OForm< 0x10, 0x2D, "cmpeq $RA,$RB,$RC",
+ [(set GPRC:$RC, (seteq GPRC:$RA, GPRC:$RB))]>;
+def CMPEQi : OFormL<0x10, 0x2D, "cmpeq $RA,$L,$RC",
+ [(set GPRC:$RC, (seteq GPRC:$RA, immUExt8:$L))]>;
+def CMPLE : OForm< 0x10, 0x6D, "cmple $RA,$RB,$RC",
+ [(set GPRC:$RC, (setle GPRC:$RA, GPRC:$RB))]>;
+def CMPLEi : OFormL<0x10, 0x6D, "cmple $RA,$L,$RC",
+ [(set GPRC:$RC, (setle GPRC:$RA, immUExt8:$L))]>;
+def CMPLT : OForm< 0x10, 0x4D, "cmplt $RA,$RB,$RC",
+ [(set GPRC:$RC, (setlt GPRC:$RA, GPRC:$RB))]>;
+def CMPLTi : OFormL<0x10, 0x4D, "cmplt $RA,$L,$RC",
+ [(set GPRC:$RC, (setlt GPRC:$RA, immUExt8:$L))]>;
+def CMPULE : OForm< 0x10, 0x3D, "cmpule $RA,$RB,$RC",
+ [(set GPRC:$RC, (setule GPRC:$RA, GPRC:$RB))]>;
+def CMPULEi : OFormL<0x10, 0x3D, "cmpule $RA,$L,$RC",
+ [(set GPRC:$RC, (setule GPRC:$RA, immUExt8:$L))]>;
+def CMPULT : OForm< 0x10, 0x1D, "cmpult $RA,$RB,$RC",
+ [(set GPRC:$RC, (setlt GPRC:$RA, GPRC:$RB))]>;
+def CMPULTi : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC",
+ [(set GPRC:$RC, (setlt GPRC:$RA, immUExt8:$L))]>;
+
+//Patterns for unsupported int comparisons
+def : Pat<(setueq GPRC:$X, GPRC:$Y), (CMPEQ GPRC:$X, GPRC:$Y)>;
+def : Pat<(setueq GPRC:$X, immUExt8:$Y), (CMPEQi GPRC:$X, immUExt8:$Y)>;
+
+def : Pat<(setugt GPRC:$X, GPRC:$Y), (CMPULT GPRC:$Y, GPRC:$X)>;
+def : Pat<(setugt immUExt8:$X, GPRC:$Y), (CMPULTi GPRC:$Y, immUExt8:$X)>;
+
+def : Pat<(setuge GPRC:$X, GPRC:$Y), (CMPULE GPRC:$Y, GPRC:$X)>;
+def : Pat<(setuge immUExt8:$X, GPRC:$Y), (CMPULEi GPRC:$Y, immUExt8:$X)>;
+
+def : Pat<(setgt GPRC:$X, GPRC:$Y), (CMPLT GPRC:$Y, GPRC:$X)>;
+def : Pat<(setgt immUExt8:$X, GPRC:$Y), (CMPLTi GPRC:$Y, immUExt8:$X)>;
+
+def : Pat<(setge GPRC:$X, GPRC:$Y), (CMPLE GPRC:$Y, GPRC:$X)>;
+def : Pat<(setge immUExt8:$X, GPRC:$Y), (CMPLEi GPRC:$Y, immUExt8:$X)>;
-//There are in the Multimedia extentions, so let's not use them yet
-def MAXSB8 : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
-def MAXSW4 : OForm< 0x1C, 0x3F, "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum
-def MAXUB8 : OForm<0x1C, 0x3C, "MAXUB8 $RA,$RB,$RC">; //Vector unsigned byte maximum
-def MAXUW4 : OForm< 0x1C, 0x3D, "MAXUW4 $RA,$RB,$RC">; //Vector unsigned word maximum
-def MINSB8 : OForm< 0x1C, 0x38, "MINSB8 $RA,$RB,$RC">; //Vector signed byte minimum
-def MINSW4 : OForm< 0x1C, 0x39, "MINSW4 $RA,$RB,$RC">; //Vector signed word minimum
-def MINUB8 : OForm< 0x1C, 0x3A, "MINUB8 $RA,$RB,$RC">; //Vector unsigned byte minimum
-def MINUW4 : OForm< 0x1C, 0x3B, "MINUW4 $RA,$RB,$RC">; //Vector unsigned word minimum
-def PERR : OForm< 0x1C, 0x31, "PERR $RA,$RB,$RC">; //Pixel error
-def PKLB : OForm< 0x1C, 0x37, "PKLB $RA,$RB,$RC">; //Pack longwords to bytes
-def PKWB : OForm<0x1C, 0x36, "PKWB $RA,$RB,$RC">; //Pack words to bytes
-def UNPKBL : OForm< 0x1C, 0x35, "UNPKBL $RA,$RB,$RC">; //Unpack bytes to longwords
-def UNPKBW : OForm< 0x1C, 0x34, "UNPKBW $RA,$RB,$RC">; //Unpack bytes to words
+def : Pat<(setne GPRC:$X, GPRC:$Y), (CMPEQi (CMPEQ GPRC:$X, GPRC:$Y), 0)>;
+def : Pat<(setne GPRC:$X, immUExt8:$Y), (CMPEQi (CMPEQi GPRC:$X, immUExt8:$Y), 0)>;
-//End operate
+def : Pat<(setune GPRC:$X, GPRC:$Y), (CMPEQi (CMPEQ GPRC:$X, GPRC:$Y), 0)>;
+def : Pat<(setune GPRC:$X, immUExt8:$Y), (CMPEQi (CMPEQ GPRC:$X, immUExt8:$Y), 0)>;
-let isReturn = 1, isTerminator = 1 in
+
+let isReturn = 1, isTerminator = 1 in
def RET : MbrForm< 0x1A, 0x02, (ops GPRC:$RD, GPRC:$RS, s64imm:$DISP), "ret $RD,($RS),$DISP">; //Return from subroutine
+//DAG Version:
+let isReturn = 1, isTerminator = 1, Ra = 31, Rb = 26, disp = 1, Uses = [R26] in
+ def RETDAG : MbrForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1">; //Return from subroutine
def JMP : MbrForm< 0x1A, 0x00, (ops GPRC:$RD, GPRC:$RS, GPRC:$DISP), "jmp $RD,($RS),$DISP">; //Jump
let isCall = 1,
@@ -267,12 +373,22 @@
def JSR : MbrForm< 0x1A, 0x01, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to subroutine
def BSR : BForm<0x34, "bsr $RA,$DISP">; //Branch to subroutine
}
+let isCall = 1,
+ Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
+ R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
+ F0, F1,
+ F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
+ F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R27, R29] in {
+ def JSRDAG : MbrForm< 0x1A, 0x01, (ops ), "jsr $$26,($$27),0">; //Jump to subroutine
+}
let isCall = 1, Defs = [R24, R25, R27, R28], Uses = [R24, R25] in
def JSRs : MbrForm< 0x1A, 0x01, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to div or rem
def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr_coroutine $RD,($RS),$DISP">; //Jump to subroutine return
def BR : BForm<0x30, "br $RA,$DISP">; //Branch
+def BR_DAG : BFormD<0x30, "br $$31,$DISP">; //Branch
+
//Stores, int
def STB : MForm<0x0E, "stb $RA,$DISP($RB)">; // Store byte
def STW : MForm<0x0D, "stw $RA,$DISP($RB)">; // Store word
@@ -349,64 +465,130 @@
def FBLT : FBForm<0x32, "fblt $RA,$DISP">; //Floating branch if < zero
def FBNE : FBForm<0x35, "fbne $RA,$DISP">; //Floating branch if != zero
-//Funky Floating point ops
-def CPYS : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC">; //Copy sign
-def CPYSE : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC">; //Copy sign and exponent
-def CPYSN : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC">; //Copy sign negate
+def RPCC : MfcForm<0x18, 0xC000, "rpcc $RA">; //Read process cycle counter
//Basic Floating point ops
-def ADDS : FPForm<0x16, 0x580, "adds/su $RA,$RB,$RC">; //Add S_floating
-def ADDT : FPForm<0x16, 0x5A0, "addt/su $RA,$RB,$RC">; //Add T_floating
-def SUBS : FPForm<0x16, 0x581, "subs/su $RA,$RB,$RC">; //Subtract S_floating
-def SUBT : FPForm<0x16, 0x5A1, "subt/su $RA,$RB,$RC">; //Subtract T_floating
-def DIVS : FPForm<0x16, 0x583, "divs/su $RA,$RB,$RC">; //Divide S_floating
-def DIVT : FPForm<0x16, 0x5A3, "divt/su $RA,$RB,$RC">; //Divide T_floating
-def MULS : FPForm<0x16, 0x582, "muls/su $RA,$RB,$RC">; //Multiply S_floating
-def MULT : FPForm<0x16, 0x5A2, "mult/su $RA,$RB,$RC">; //Multiply T_floating
-def SQRTS : FPForm<0x14, 0x58B, "sqrts/su $RA,$RB,$RC">; //Square root S_floating
-def SQRTT : FPForm<0x14, 0x5AB, "sqrtt/su $RA,$RB,$RC">; //Square root T_floating
-
-//INT reg to FP reg and back again
-//not supported on 21164
-def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC">; //Floating to integer move, S_floating
-def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC">; //Floating to integer move, T_floating
-def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC">; //Integer to floating move, S_floating
-def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC">; //Integer to floating move, T_floating
-//CVTLQ F-P 17.010 Convert longword to quadword
-//CVTQL F-P 17.030 Convert quadword to longword
-//These use SW completion, may not have function code for that set right (matters for JIT)
-def CVTQS : FPForm<0x16, 0x0BC, "cvtqs $RB,$RC">; //Convert quadword to S_floating
-def CVTQT : FPForm<0x16, 0x0BE, "cvtqt $RB,$RC">; //Convert quadword to T_floating
-def CVTST : FPForm<0x16, 0x2AC, "cvtsts $RB,$RC">; //Convert S_floating to T_floating
-def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC">; //Convert T_floating to quadword
-def CVTTS : FPForm<0x16, 0x5AC, "cvtts/su $RB,$RC">; //Convert T_floating to S_floating
+//Floats
+
+let OperandList = (ops F4RC:$RC, F4RC:$RB), Fa = 31 in
+def SQRTS : FPForm<0x14, 0x58B, "sqrts/su $RB,$RC",
+ [(set F4RC:$RC, (fsqrt F4RC:$RB))]>;
+
+let OperandList = (ops F4RC:$RC, F4RC:$RA, F4RC:$RB) in {
+def ADDS : FPForm<0x16, 0x580, "adds/su $RA,$RB,$RC",
+ [(set F4RC:$RC, (fadd F4RC:$RA, F4RC:$RB))]>;
+def SUBS : FPForm<0x16, 0x581, "subs/su $RA,$RB,$RC",
+ [(set F4RC:$RC, (fsub F4RC:$RA, F4RC:$RB))]>;
+def DIVS : FPForm<0x16, 0x583, "divs/su $RA,$RB,$RC",
+ [(set F4RC:$RC, (fdiv F4RC:$RA, F4RC:$RB))]>;
+def MULS : FPForm<0x16, 0x582, "muls/su $RA,$RB,$RC",
+ [(set F4RC:$RC, (fmul F4RC:$RA, F4RC:$RB))]>;
+
+def CPYSS : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",[]>; //Copy sign
+def CPYSES : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[]>; //Copy sign and exponent
+def CPYSNS : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",[]>; //Copy sign negate
+}
+
+//Doubles
+
+let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in
+def SQRTT : FPForm<0x14, 0x5AB, "sqrtt/su $RB,$RC",
+ [(set F8RC:$RC, (fsqrt F8RC:$RB))]>;
+
+let OperandList = (ops F8RC:$RC, F8RC:$RA, F8RC:$RB) in {
+def ADDT : FPForm<0x16, 0x5A0, "addt/su $RA,$RB,$RC",
+ [(set F8RC:$RC, (fadd F8RC:$RA, F8RC:$RB))]>;
+def SUBT : FPForm<0x16, 0x5A1, "subt/su $RA,$RB,$RC",
+ [(set F8RC:$RC, (fsub F8RC:$RA, F8RC:$RB))]>;
+def DIVT : FPForm<0x16, 0x5A3, "divt/su $RA,$RB,$RC",
+ [(set F8RC:$RC, (fdiv F8RC:$RA, F8RC:$RB))]>;
+def MULT : FPForm<0x16, 0x5A2, "mult/su $RA,$RB,$RC",
+ [(set F8RC:$RC, (fmul F8RC:$RA, F8RC:$RB))]>;
+
+def CPYST : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",[]>; //Copy sign
+def CPYSET : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[]>; //Copy sign and exponent
+def CPYSNT : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",[]>; //Copy sign negate
+
+def CMPTEQ : FPForm<0x16, 0x5A5, "cmpteq/su $RA,$RB,$RC", []>;
+// [(set F8RC:$RC, (seteq F8RC:$RA, F8RC:$RB))]>;
+def CMPTLE : FPForm<0x16, 0x5A7, "cmptle/su $RA,$RB,$RC", []>;
+// [(set F8RC:$RC, (setle F8RC:$RA, F8RC:$RB))]>;
+def CMPTLT : FPForm<0x16, 0x5A6, "cmptlt/su $RA,$RB,$RC", []>;
+// [(set F8RC:$RC, (setlt F8RC:$RA, F8RC:$RB))]>;
+def CMPTUN : FPForm<0x16, 0x5A4, "cmptun/su $RA,$RB,$RC", []>;
+// [(set F8RC:$RC, (setuo F8RC:$RA, F8RC:$RB))]>;
+}
+//TODO: Add lots more FP patterns
+
+
+
+let OperandList = (ops GPRC:$RC, F4RC:$RA), Fb = 31 in
+def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC",[]>; //Floating to integer move, S_floating
+let OperandList = (ops GPRC:$RC, F8RC:$RA), Fb = 31 in
+def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC",[]>; //Floating to integer move, T_floating
+let OperandList = (ops F4RC:$RC, GPRC:$RA), Fb = 31 in
+def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC",[]>; //Integer to floating move, S_floating
+let OperandList = (ops F8RC:$RC, GPRC:$RA), Fb = 31 in
+def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC",[]>; //Integer to floating move, T_floating
+
+
+let OperandList = (ops F4RC:$RC, F8RC:$RB), Fa = 31 in
+def CVTQS : FPForm<0x16, 0x7BC, "cvtqs/sui $RB,$RC",[]>; //Convert quadword to S_floating
+let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in
+def CVTQT : FPForm<0x16, 0x7BE, "cvtqt/sui $RB,$RC",[]>; //Convert quadword to T_floating
+let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in
+def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC",[]>; //Convert T_floating to quadword
+let OperandList = (ops F8RC:$RC, F4RC:$RB), Fa = 31 in
+def CVTST : FPForm<0x16, 0x6AC, "cvtst/s $RB,$RC",
+ [(set F8RC:$RC, (fextend F4RC:$RB))]>;
+let OperandList = (ops F4RC:$RC, F8RC:$RB), Fa = 31 in
+def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC",
+ [(set F4RC:$RC, (fround F8RC:$RB))]>;
//S_floating : IEEE Single
//T_floating : IEEE Double
+//Unused instructions
//Mnemonic Format Opcode Description
-
//CALL_PAL Pcd 00 Trap to PALcode
//ECB Mfc 18.E800 Evict cache block
//EXCB Mfc 18.0400 Exception barrier
//FETCH Mfc 18.8000 Prefetch data
//FETCH_M Mfc 18.A000 Prefetch data, modify intent
-
//LDL_L Mem 2A Load sign-extended longword locked
//LDQ_L Mem 2B Load quadword locked
//LDQ_U Mem 0B Load unaligned quadword
//MB Mfc 18.4000 Memory barrier
-//RPCC Mfc 18.C000 Read process cycle counter
-
//STL_C Mem 2E Store longword conditional
//STQ_C Mem 2F Store quadword conditional
//STQ_U Mem 0F Store unaligned quadword
-
//TRAPB Mfc 18.0000 Trap barrier
//WH64 Mfc 18.F800 Write hint 64 bytes
//WMB Mfc 18.4400 Write memory barrier
-
-
//MF_FPCR F-P 17.025 Move from FPCR
//MT_FPCR F-P 17.024 Move to FPCR
+//There are in the Multimedia extentions, so let's not use them yet
+//def MAXSB8 : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
+//def MAXSW4 : OForm< 0x1C, 0x3F, "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum
+//def MAXUB8 : OForm<0x1C, 0x3C, "MAXUB8 $RA,$RB,$RC">; //Vector unsigned byte maximum
+//def MAXUW4 : OForm< 0x1C, 0x3D, "MAXUW4 $RA,$RB,$RC">; //Vector unsigned word maximum
+//def MINSB8 : OForm< 0x1C, 0x38, "MINSB8 $RA,$RB,$RC">; //Vector signed byte minimum
+//def MINSW4 : OForm< 0x1C, 0x39, "MINSW4 $RA,$RB,$RC">; //Vector signed word minimum
+//def MINUB8 : OForm< 0x1C, 0x3A, "MINUB8 $RA,$RB,$RC">; //Vector unsigned byte minimum
+//def MINUW4 : OForm< 0x1C, 0x3B, "MINUW4 $RA,$RB,$RC">; //Vector unsigned word minimum
+//def PERR : OForm< 0x1C, 0x31, "PERR $RA,$RB,$RC">; //Pixel error
+//def PKLB : OForm< 0x1C, 0x37, "PKLB $RA,$RB,$RC">; //Pack longwords to bytes
+//def PKWB : OForm<0x1C, 0x36, "PKWB $RA,$RB,$RC">; //Pack words to bytes
+//def UNPKBL : OForm< 0x1C, 0x35, "UNPKBL $RA,$RB,$RC">; //Unpack bytes to longwords
+//def UNPKBW : OForm< 0x1C, 0x34, "UNPKBW $RA,$RB,$RC">; //Unpack bytes to words
+//CVTLQ F-P 17.010 Convert longword to quadword
+//CVTQL F-P 17.030 Convert quadword to longword
+//def AMASK : OForm< 0x11, 0x61, "AMASK $RA,$RB,$RC", []>; //Architecture mask
+//def AMASKi : OFormL<0x11, 0x61, "AMASK $RA,$L,$RC", []>; //Architecture mask
+
+
+
+
+def : Pat<(i64 immSExt16:$imm),
+ (LDA immSExt16:$imm, R31)>;
Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.28 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.28.2.1
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.28 Sun Oct 9 15:11:35 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Wed Nov 16 12:32:33 2005
@@ -65,13 +65,6 @@
{
}
-static const TargetRegisterClass *getClass(unsigned SrcReg) {
- if (Alpha::FPRCRegisterClass->contains(SrcReg))
- return Alpha::FPRCRegisterClass;
- assert(Alpha::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
- return Alpha::GPRCRegisterClass;
-}
-
void
AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
@@ -82,9 +75,11 @@
if (EnableAlphaLSMark)
BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(1)
.addImm(getUID());
- if (getClass(SrcReg) == Alpha::FPRCRegisterClass)
+ if (RC == Alpha::F4RCRegisterClass)
+ BuildMI(MBB, MI, Alpha::STS, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else if (RC == Alpha::F8RCRegisterClass)
BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
- else if (getClass(SrcReg) == Alpha::GPRCRegisterClass)
+ else if (RC == Alpha::GPRCRegisterClass)
BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else
abort();
@@ -99,9 +94,11 @@
if (EnableAlphaLSMark)
BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2)
.addImm(getUID());
- if (getClass(DestReg) == Alpha::FPRCRegisterClass)
+ if (RC == Alpha::F4RCRegisterClass)
+ BuildMI(MBB, MI, Alpha::LDS, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else if (RC == Alpha::F8RCRegisterClass)
BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
- else if (getClass(DestReg) == Alpha::GPRCRegisterClass)
+ else if (RC == Alpha::GPRCRegisterClass)
BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else
abort();
@@ -126,6 +123,50 @@
return 0;
}
+MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
+ unsigned OpNum,
+ int FrameIndex) const {
+ // Make sure this is a reg-reg copy.
+ unsigned Opc = MI->getOpcode();
+
+ if ((Opc == Alpha::BIS &&
+ MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
+ if (OpNum == 0) { // move -> store
+ unsigned InReg = MI->getOperand(1).getReg();
+ return BuildMI(Alpha::STQ, 3).addReg(InReg).addFrameIndex(FrameIndex)
+ .addReg(Alpha::F31);
+ } else { // load -> move
+ unsigned OutReg = MI->getOperand(0).getReg();
+ return BuildMI(Alpha::LDQ, 2, OutReg).addFrameIndex(FrameIndex)
+ .addReg(Alpha::F31);
+ }
+ } else if ((Opc == Alpha::CPYSS &&
+ MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
+ if (OpNum == 0) { // move -> store
+ unsigned InReg = MI->getOperand(1).getReg();
+ return BuildMI(Alpha::STS, 3).addReg(InReg).addFrameIndex(FrameIndex)
+ .addReg(Alpha::F31);
+ } else { // load -> move
+ unsigned OutReg = MI->getOperand(0).getReg();
+ return BuildMI(Alpha::LDS, 2, OutReg).addFrameIndex(FrameIndex)
+ .addReg(Alpha::F31);
+ }
+ } else if ((Opc == Alpha::CPYST &&
+ MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
+ if (OpNum == 0) { // move -> store
+ unsigned InReg = MI->getOperand(1).getReg();
+ return BuildMI(Alpha::STT, 3).addReg(InReg).addFrameIndex(FrameIndex)
+ .addReg(Alpha::F31);
+ } else { // load -> move
+ unsigned OutReg = MI->getOperand(0).getReg();
+ return BuildMI(Alpha::LDT, 2, OutReg).addFrameIndex(FrameIndex)
+ .addReg(Alpha::F31);
+ }
+ }
+ return 0;
+}
+
+
void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
@@ -133,8 +174,10 @@
// std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
if (RC == Alpha::GPRCRegisterClass) {
BuildMI(MBB, MI, Alpha::BIS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
- } else if (RC == Alpha::FPRCRegisterClass) {
- BuildMI(MBB, MI, Alpha::CPYS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ } else if (RC == Alpha::F4RCRegisterClass) {
+ BuildMI(MBB, MI, Alpha::CPYSS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ } else if (RC == Alpha::F8RCRegisterClass) {
+ BuildMI(MBB, MI, Alpha::CPYST, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
} else {
std::cerr << "Attempt to copy register that is not GPR or FPR";
abort();
@@ -314,7 +357,7 @@
MachineBasicBlock &MBB) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
- assert((MBBI->getOpcode() == Alpha::RET)
+ assert(((MBBI->getOpcode() == Alpha::RET) || (MBBI->getOpcode() == Alpha::RETDAG))
&& "Can only insert epilog into returning blocks");
bool FP = hasFP(MF);
Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.h
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.7 llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.7.2.1
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.7 Sun Oct 9 15:11:35 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.h Wed Nov 16 12:32:33 2005
@@ -37,6 +37,9 @@
virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
+ MachineInstr* foldMemoryOperand(MachineInstr *MI, unsigned OpNum,
+ int FrameIndex) const;
+
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.td
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.12 llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.12.2.1
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.12 Fri Aug 19 13:50:46 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.td Wed Nov 16 12:32:33 2005
@@ -82,20 +82,59 @@
def GPRC : RegisterClass<"Alpha", i64, 64,
// Volatile
[R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
- R23, R24, R25,
+ R23, R24, R25, R28,
//Special meaning, but volatile
R27, //procedure address
R26, //return address
R29, //global offset table address
// Non-volatile
- R9, R10, R11, R12, R13, R14 ]>;
- // Note: R28 is reserved for the assembler
+ R9, R10, R11, R12, R13, R14,
+ R31 ]> //zero
+{
+ let MethodProtos = [{
+ iterator allocation_order_end(MachineFunction &MF) const;
+ }];
+ let MethodBodies = [{
+ GPRCClass::iterator
+ GPRCClass::allocation_order_end(MachineFunction &MF) const {
+ return end()-1;
+ }
+ }];
+}
-// Don't allocate 15, 29, 30, 31
-// Allocation volatiles only for now
-def FPRC : RegisterClass<"Alpha", f64, 64, [F0, F1,
+def F4RC : RegisterClass<"Alpha", f32, 64, [F0, F1,
F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
// Saved:
- F2, F3, F4, F5, F6, F7, F8, F9
- ]>;
+ F2, F3, F4, F5, F6, F7, F8, F9,
+ F31 ]> //zero
+{
+ let MethodProtos = [{
+ iterator allocation_order_end(MachineFunction &MF) const;
+ }];
+ let MethodBodies = [{
+ F4RCClass::iterator
+ F4RCClass::allocation_order_end(MachineFunction &MF) const {
+ return end()-1;
+ }
+ }];
+}
+
+def F8RC : RegisterClass<"Alpha", f64, 64, [F0, F1,
+ F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
+ F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
+ // Saved:
+ F2, F3, F4, F5, F6, F7, F8, F9,
+ F31 ]> //zero
+{
+ let MethodProtos = [{
+ iterator allocation_order_end(MachineFunction &MF) const;
+ }];
+ let MethodBodies = [{
+ F8RCClass::iterator
+ F8RCClass::allocation_order_end(MachineFunction &MF) const {
+ return end()-1;
+ }
+ }];
+}
+
Index: llvm/lib/Target/Alpha/AlphaSubtarget.cpp
diff -u llvm/lib/Target/Alpha/AlphaSubtarget.cpp:1.3 llvm/lib/Target/Alpha/AlphaSubtarget.cpp:1.3.2.1
--- llvm/lib/Target/Alpha/AlphaSubtarget.cpp:1.3 Sun Oct 2 02:13:52 2005
+++ llvm/lib/Target/Alpha/AlphaSubtarget.cpp Wed Nov 16 12:32:33 2005
@@ -13,49 +13,13 @@
#include "AlphaSubtarget.h"
#include "Alpha.h"
-#include "llvm/Module.h"
-#include "llvm/Support/CommandLine.h"
-#include "llvm/Target/SubtargetFeature.h"
-#include "llvm/Support/Debug.h"
-
+#include "AlphaGenSubtarget.inc"
using namespace llvm;
-enum AlphaFeature {
- AlphaFeatureCIX = 1 << 0,
- AlphaFeatureFIX = 1 << 1,
-};
-
-/// Sorted (by key) array of values for CPU subtype.
-static const SubtargetFeatureKV AlphaSubTypeKV[] = {
- { "ev56" , "Select the Alpha EV56 processor", 0 },
- { "ev6" , "Select the Alpha EV6 processor", AlphaFeatureFIX },
- { "ev67" , "Select the Alpha EV67 processor", AlphaFeatureFIX | AlphaFeatureCIX },
- { "generic", "Select instructions for a generic Alpha processor (EV56)", 0 },
- { "pca56" , "Select the Alpha PCA56 processor", 0 },
-};
-
-/// Length of AlphaSubTypeKV.
-static const unsigned AlphaSubTypeKVSize = sizeof(AlphaSubTypeKV)
- / sizeof(SubtargetFeatureKV);
-
-/// Sorted (by key) array of values for CPU features.
-static SubtargetFeatureKV AlphaFeatureKV[] = {
- { "CIX", "Should CIX extentions be used" , AlphaFeatureCIX },
- { "FIX" , "Should FIX extentions be used" , AlphaFeatureFIX },
- };
-/// Length of AlphaFeatureKV.
-static const unsigned AlphaFeatureKVSize = sizeof(AlphaFeatureKV)
- / sizeof(SubtargetFeatureKV);
-
AlphaSubtarget::AlphaSubtarget(const Module &M, const std::string &FS)
- :HasF2I(false), HasCT(false)
-{
+ : HasF2I(false), HasCT(false) {
std::string CPU = "generic";
- uint32_t Bits =
- SubtargetFeatures::Parse(FS, CPU,
- AlphaSubTypeKV, AlphaSubTypeKVSize,
- AlphaFeatureKV, AlphaFeatureKVSize);
- HasF2I = (Bits & AlphaFeatureFIX) != 0;
- HasCT = (Bits & AlphaFeatureCIX) != 0;
+ // Parse features string.
+ ParseSubtargetFeatures(FS, CPU);
}
Index: llvm/lib/Target/Alpha/AlphaSubtarget.h
diff -u llvm/lib/Target/Alpha/AlphaSubtarget.h:1.1 llvm/lib/Target/Alpha/AlphaSubtarget.h:1.1.2.1
--- llvm/lib/Target/Alpha/AlphaSubtarget.h:1.1 Thu Sep 29 17:54:56 2005
+++ llvm/lib/Target/Alpha/AlphaSubtarget.h Wed Nov 16 12:32:33 2005
@@ -33,6 +33,10 @@
/// of the specified module.
///
AlphaSubtarget(const Module &M, const std::string &FS);
+
+ /// ParseSubtargetFeatures - Parses features string setting specified
+ /// subtarget options. Definition of function is auto generated by tblgen.
+ void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
bool hasF2I() const { return HasF2I; }
bool hasCT() const { return HasCT; }
Index: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.13 llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.13.2.1
--- llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.13 Thu Sep 29 17:54:56 2005
+++ llvm/lib/Target/Alpha/AlphaTargetMachine.cpp Wed Nov 16 12:32:33 2005
@@ -29,8 +29,8 @@
}
namespace llvm {
- cl::opt<bool> EnableAlphaLSR("enable-lsr-for-alpha",
- cl::desc("Enable LSR for Alpha (beta option!)"),
+ cl::opt<bool> EnableAlphaDAG("enable-dag-isel-for-alpha",
+ cl::desc("Enable DAG ISEL for Alpha (beta option!)"),
cl::Hidden);
}
@@ -48,7 +48,7 @@
M.getPointerSize() != Module::AnyPointerSize)
return 0; // Match for some other target
- return 0;
+ return getJITMatchQuality()/2;
}
unsigned AlphaTargetMachine::getJITMatchQuality() {
@@ -74,13 +74,11 @@
///
bool AlphaTargetMachine::addPassesToEmitFile(PassManager &PM,
std::ostream &Out,
- CodeGenFileType FileType) {
+ CodeGenFileType FileType,
+ bool Fast) {
if (FileType != TargetMachine::AssemblyFile) return true;
- if (EnableAlphaLSR) {
- PM.add(createLoopStrengthReducePass());
- PM.add(createCFGSimplificationPass());
- }
+ PM.add(createLoopStrengthReducePass());
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());
@@ -94,7 +92,12 @@
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
- PM.add(createAlphaPatternInstructionSelector(*this));
+ PM.add(createCFGSimplificationPass());
+
+ if (EnableAlphaDAG)
+ PM.add(createAlphaISelDag(*this));
+ else
+ PM.add(createAlphaPatternInstructionSelector(*this));
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(&std::cerr));
@@ -117,10 +120,8 @@
void AlphaJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
- if (EnableAlphaLSR) {
- PM.add(createLoopStrengthReducePass());
- PM.add(createCFGSimplificationPass());
- }
+ PM.add(createLoopStrengthReducePass());
+ PM.add(createCFGSimplificationPass());
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());
Index: llvm/lib/Target/Alpha/AlphaTargetMachine.h
diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.10 llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.10.2.1
--- llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.10 Thu Sep 29 17:54:56 2005
+++ llvm/lib/Target/Alpha/AlphaTargetMachine.h Wed Nov 16 12:32:33 2005
@@ -48,17 +48,11 @@
static unsigned getJITMatchQuality();
- /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
- /// get machine code emitted. This uses a MachineCodeEmitter object to handle
- /// actually outputting the machine code and resolving things like the address
- /// of functions. This method should returns true if machine code emission is
- /// not supported.
- ///
virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE);
virtual bool addPassesToEmitFile(PassManager &PM, std::ostream &Out,
- CodeGenFileType FileType);
+ CodeGenFileType FileType, bool Fast);
static unsigned getModuleMatchQuality(const Module &M);
};
Index: llvm/lib/Target/Alpha/Makefile
diff -u llvm/lib/Target/Alpha/Makefile:1.2 llvm/lib/Target/Alpha/Makefile:1.2.4.1
--- llvm/lib/Target/Alpha/Makefile:1.2 Mon Feb 21 22:58:26 2005
+++ llvm/lib/Target/Alpha/Makefile Wed Nov 16 12:32:33 2005
@@ -14,6 +14,7 @@
BUILT_SOURCES = AlphaGenRegisterInfo.h.inc AlphaGenRegisterNames.inc \
AlphaGenRegisterInfo.inc AlphaGenInstrNames.inc \
AlphaGenInstrInfo.inc AlphaGenCodeEmitter.inc \
- AlphaGenAsmWriter.inc
+ AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
+ AlphaGenSubtarget.inc
include $(LEVEL)/Makefile.common
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