[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp

[Andrew Lenharth]

Changes in directory llvm/lib/Target/Alpha:

AlphaTargetMachine.cpp updated: 1.16 -> 1.17
---
Log message:

enable LSR by default on alpha

---
Diffs of the changes:  (+3 -7)

 AlphaTargetMachine.cpp |   10 +++-------
 1 files changed, 3 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.16 llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.17
--- llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.16	Mon Nov  7 20:11:51 2005
+++ llvm/lib/Target/Alpha/AlphaTargetMachine.cpp	Sat Nov 12 13:21:08 2005
@@ -29,9 +29,6 @@
 }
 
 namespace llvm {
-  cl::opt<bool> EnableAlphaLSR("enable-lsr-for-alpha",
-                             cl::desc("Enable LSR for Alpha (beta option!)"),
-                             cl::Hidden);
   cl::opt<bool> EnableAlphaDAG("enable-dag-isel-for-alpha",
                              cl::desc("Enable DAG ISEL for Alpha (beta option!)"),
                              cl::Hidden);
@@ -81,10 +78,7 @@
                                              bool Fast) {
   if (FileType != TargetMachine::AssemblyFile) return true;
 
-  if (EnableAlphaLSR) {
-    PM.add(createLoopStrengthReducePass());
-    PM.add(createCFGSimplificationPass());
-  }
+  PM.add(createLoopStrengthReducePass());
 
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());
@@ -98,6 +92,8 @@
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
+  PM.add(createCFGSimplificationPass());
+
   if (EnableAlphaDAG)
     PM.add(createAlphaISelDag(*this));
   else