[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Jeff Cohen
jeffc at jolt-lang.org
Fri Nov 11 16:59:12 PST 2005
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.61 -> 1.62
---
Log message:
Fix operator precedence bug caught by VC++.
---
Diffs of the changes: (+2 -2)
DAGCombiner.cpp | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.61 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.62
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.61 Wed Nov 9 17:47:37 2005
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Nov 11 18:59:01 2005
@@ -967,8 +967,8 @@
// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
if (N1C && N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
unsigned ExtendBits =
- MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
- if (ExtendBits == 64 || (N1C->getValue() & (~0ULL << ExtendBits) == 0))
+ MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
+ if (ExtendBits == 64 || ((N1C->getValue() & (~0ULL << ExtendBits)) == 0))
return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
}
// fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
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