[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

[Duraid Madina]

Changes in directory llvm/lib/Target/IA64:

IA64InstrInfo.td updated: 1.21 -> 1.22
---
Log message:

add support for int->FP and FP->int ops, and add ia64 patterns for these 



---
Diffs of the changes:  (+12 -0)

 IA64InstrInfo.td |   12 ++++++++++++
 1 files changed, 12 insertions(+)


Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.21 llvm/lib/Target/IA64/IA64InstrInfo.td:1.22
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.21	Mon Oct 31 19:29:55 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td	Mon Oct 31 21:07:25 2005
@@ -553,6 +553,18 @@
 def SETFSIG : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
   "setf.sig $dst = $src;;">;
 
+// these four FP<->int conversion patterns need checking/cleaning
+def SINT_TO_FP : Pat<(sint_to_fp GR:$src),
+  (FNORMD (FCVTXF (SETFSIG GR:$src)))>;
+def UINT_TO_FP : Pat<(uint_to_fp GR:$src),
+  (FNORMD (FCVTXUF (SETFSIG GR:$src)))>;
+/* FIXME: tablegen coughs on these
+def FP_TO_SINT : Pat<(fp_to_sint FP:$src),
+  (GETFSIG (FCVTFXTRUNC FP:$src))>;
+def FP_TO_UINT : Pat<(fp_to_uint FP:$src),
+  (GETFSIG (FCVTFXUTRUNC FP:$src))>;
+*/
+
 let isTerminator = 1, isBranch = 1 in {
   def BRL_NOTCALL : RawForm<0x03, 0xb0, (ops i64imm:$dst),
     "(p0) brl.cond.sptk $dst;;">;