[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.57 -> 1.58
---
Log message:

Codegen mul by negative power of two with a shift and negate.
This implements test/Regression/CodeGen/PowerPC/mul-neg-power-2.ll,
producing:

_foo:
        slwi r2, r3, 1
        subfic r3, r2, 63
        blr

instead of:

_foo:
        mulli r2, r3, -2
        addi r3, r2, 63
        blr



---
Diffs of the changes:  (+13 -3)

 DAGCombiner.cpp |   16 +++++++++++++---
 1 files changed, 13 insertions(+), 3 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.57 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.58
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.57	Thu Oct 27 02:10:34 2005
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Sun Oct 30 01:41:49 2005
@@ -735,8 +735,7 @@
   
   // fold (mul c1, c2) -> c1*c2
   if (N0C && N1C)
-    return DAG.getConstant(N0C->getValue() * N1C->getValue(),
-                           N->getValueType(0));
+    return DAG.getConstant(N0C->getValue() * N1C->getValue(), VT);
   // canonicalize constant to RHS
   if (N0C && !N1C)
     return DAG.getNode(ISD::MUL, VT, N1, N0);
@@ -748,9 +747,20 @@
     return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
   // fold (mul x, (1 << c)) -> x << c
   if (N1C && isPowerOf2_64(N1C->getValue()))
-    return DAG.getNode(ISD::SHL, N->getValueType(0), N0,
+    return DAG.getNode(ISD::SHL, VT, N0,
                        DAG.getConstant(Log2_64(N1C->getValue()),
                                        TLI.getShiftAmountTy()));
+  // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
+  if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
+    // FIXME: If the input is something that is easily negated (e.g. a 
+    // single-use add), we should put the negate there.
+    return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
+                       DAG.getNode(ISD::SHL, VT, N0,
+                            DAG.getConstant(Log2_64(-N1C->getSignExtended()),
+                                            TLI.getShiftAmountTy())));
+  }
+  
+  
   // fold (mul (mul x, c1), c2) -> (mul x, c1*c2)
   if (N1C && N0.getOpcode() == ISD::MUL) {
     ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));