[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC.td

[Jim Laskey]

Changes in directory llvm/lib/Target/PowerPC:

PPC.td updated: 1.5 -> 1.6
---
Log message:

Add g3 back to the mix and reorder to irritate them anal folk.  Actually, it's
to group appropriately and provide cues to maintainers that the lists don't 
need to be ordered.


---
Diffs of the changes:  (+10 -9)

 PPC.td |   19 ++++++++++---------
 1 files changed, 10 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC.td
diff -u llvm/lib/Target/PowerPC/PPC.td:1.5 llvm/lib/Target/PowerPC/PPC.td:1.6
--- llvm/lib/Target/PowerPC/PPC.td:1.5	Fri Oct 21 17:15:43 2005
+++ llvm/lib/Target/PowerPC/PPC.td	Sat Oct 22 03:04:24 2005
@@ -26,7 +26,7 @@
 
 
 //===----------------------------------------------------------------------===//
-// PowerPC Subtarget features (sorted by name).
+// PowerPC Subtarget features.
 //
  
 def Feature64Bit     : SubtargetFeature<"64bit",
@@ -35,15 +35,16 @@
                                 "Should 64 bit registers be used">;
 def FeatureAltivec   : SubtargetFeature<"altivec",
                                 "Should Altivec instructions be used">;
-def FeatureFSqrt     : SubtargetFeature<"fsqrt",
-                                "Should the fsqrt instruction be used">; 
 def FeatureGPUL      : SubtargetFeature<"gpul",
                                 "Should GPUL instructions be used">;
+def FeatureFSqrt     : SubtargetFeature<"fsqrt",
+                                "Should the fsqrt instruction be used">; 
 
 //===----------------------------------------------------------------------===//
-// PowerPC chips sets supported (sorted by name)
+// PowerPC chips sets supported.
 //
 
+def : Processor<"generic", G3Itineraries, []>;
 def : Processor<"601", G3Itineraries, []>;
 def : Processor<"602", G3Itineraries, []>;
 def : Processor<"603", G3Itineraries, []>;
@@ -52,18 +53,18 @@
 def : Processor<"604", G3Itineraries, []>;
 def : Processor<"604e", G3Itineraries, []>;
 def : Processor<"620", G3Itineraries, []>;
+def : Processor<"g3", G3Itineraries, []>;
 def : Processor<"7400", G4Itineraries, [FeatureAltivec]>;
+def : Processor<"g4", G4Itineraries, [FeatureAltivec]>;
 def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
+def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
 def : Processor<"750", G3Itineraries, []>;
 def : Processor<"970", G5Itineraries,
                   [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
-                   Feature64Bit /*, Feature64BitRegs*/]>;
-def : Processor<"g4", G4Itineraries, [FeatureAltivec]>;
-def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
+                   Feature64Bit /*, Feature64BitRegs */]>;
 def : Processor<"g5", G5Itineraries,
                   [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
-                   Feature64Bit /*, Feature64BitRegs*/]>;
-def : Processor<"generic", G3Itineraries, []>;
+                   Feature64Bit /*, Feature64BitRegs */]>;
 
 
 def PPC : Target {