[llvm-commits] CVS: llvm/lib/Target/PowerPC/Makefile PPC.td PPCSubtarget.cpp
Jim Laskey
jlaskey at apple.com
Fri Oct 21 12:02:57 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
Makefile updated: 1.20 -> 1.21
PPC.td updated: 1.3 -> 1.4
PPCSubtarget.cpp updated: 1.10 -> 1.11
---
Log message:
Plugin new subtarget backend into the build.
---
Diffs of the changes: (+39 -77)
Makefile | 2 -
PPC.td | 43 +++++++++++++++++++--------------
PPCSubtarget.cpp | 71 ++++++++++---------------------------------------------
3 files changed, 39 insertions(+), 77 deletions(-)
Index: llvm/lib/Target/PowerPC/Makefile
diff -u llvm/lib/Target/PowerPC/Makefile:1.20 llvm/lib/Target/PowerPC/Makefile:1.21
--- llvm/lib/Target/PowerPC/Makefile:1.20 Fri Oct 14 18:37:35 2005
+++ llvm/lib/Target/PowerPC/Makefile Fri Oct 21 14:02:44 2005
@@ -14,6 +14,6 @@
BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \
PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \
PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \
- PPCGenInstrInfo.inc PPCGenDAGISel.inc
+ PPCGenInstrInfo.inc PPCGenDAGISel.inc PPCGenSubtarget.inc
include $(LEVEL)/Makefile.common
Index: llvm/lib/Target/PowerPC/PPC.td
diff -u llvm/lib/Target/PowerPC/PPC.td:1.3 llvm/lib/Target/PowerPC/PPC.td:1.4
--- llvm/lib/Target/PowerPC/PPC.td:1.3 Wed Oct 19 14:51:16 2005
+++ llvm/lib/Target/PowerPC/PPC.td Fri Oct 21 14:02:44 2005
@@ -26,37 +26,44 @@
//===----------------------------------------------------------------------===//
-// PowerPC Subtarget features.
+// PowerPC Subtarget features (sorted by name).
//
-def F64Bit : SubtargetFeature<"64bit",
- "Should 64 bit instructions be used">;
-def F64BitRegs : SubtargetFeature<"64bitregs",
- "Should 64 bit registers be used">;
-def FAltivec : SubtargetFeature<"altivec",
- "Should Altivec instructions be used">;
-def FGPUL : SubtargetFeature<"gpul",
- "Should GPUL instructions be used">;
-def FFSQRT : SubtargetFeature<"fsqrt",
- "Should the fsqrt instruction be used">;
+def Feature64Bit : SubtargetFeature<"64bit",
+ "Should 64 bit instructions be used">;
+def Feature64BitRegs : SubtargetFeature<"64bitregs",
+ "Should 64 bit registers be used">;
+def FeatureAltivec : SubtargetFeature<"altivec",
+ "Should Altivec instructions be used">;
+def FeatureFSqrt : SubtargetFeature<"fsqrt",
+ "Should the fsqrt instruction be used">;
+def FeatureGPUL : SubtargetFeature<"gpul",
+ "Should GPUL instructions be used">;
//===----------------------------------------------------------------------===//
-// PowerPC chips sets supported
+// PowerPC chips sets supported (sorted by name)
//
def : Processor<"601", G3Itineraries, []>;
def : Processor<"602", G3Itineraries, []>;
def : Processor<"603", G3Itineraries, []>;
+def : Processor<"603e", G3Itineraries, []>;
+def : Processor<"603ev", G3Itineraries, []>;
def : Processor<"604", G3Itineraries, []>;
+def : Processor<"604e", G3Itineraries, []>;
+def : Processor<"620", G3Itineraries, []>;
+def : Processor<"7400", G4Itineraries, [FeatureAltivec]>;
+def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
def : Processor<"750", G3Itineraries, []>;
-def : Processor<"7400", G4Itineraries, [FAltivec]>;
-def : Processor<"g4", G4Itineraries, [FAltivec]>;
-def : Processor<"7450", G4PlusItineraries, [FAltivec]>;
-def : Processor<"g4+", G4PlusItineraries, [FAltivec]>;
def : Processor<"970", G5Itineraries,
- [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;
+ [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
+ Feature64Bit, Feature64BitRegs]>;
+def : Processor<"g4", G4Itineraries, [FeatureAltivec]>;
+def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
def : Processor<"g5", G5Itineraries,
- [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;
+ [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
+ Feature64Bit, Feature64BitRegs]>;
+def : Processor<"generic", G3Itineraries, []>;
def PPC : Target {
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
diff -u llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.10 llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.11
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.10 Mon Oct 17 19:56:42 2005
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp Fri Oct 21 14:02:44 2005
@@ -16,6 +16,7 @@
#include "llvm/Module.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/SubtargetFeature.h"
+#include "PPCGenSubtarget.inc"
using namespace llvm;
PPCTargetEnum llvm::PPCTarget = TargetDefault;
@@ -29,59 +30,14 @@
" Enable Darwin codegen"),
clEnumValEnd),
cl::location(PPCTarget), cl::init(TargetDefault));
-}
-
-enum PowerPCFeature {
- PowerPCFeature64Bit = 1 << 0,
- PowerPCFeatureAltivec = 1 << 1,
- PowerPCFeatureFSqrt = 1 << 2,
- PowerPCFeatureGPUL = 1 << 3,
- PowerPCFeature64BRegs = 1 << 4
-};
-
-/// Sorted (by key) array of values for CPU subtype.
-static const SubtargetFeatureKV PowerPCSubTypeKV[] = {
- { "601" , "Select the PowerPC 601 processor", 0 },
- { "602" , "Select the PowerPC 602 processor", 0 },
- { "603" , "Select the PowerPC 603 processor", 0 },
- { "603e" , "Select the PowerPC 603e processor", 0 },
- { "603ev" , "Select the PowerPC 603ev processor", 0 },
- { "604" , "Select the PowerPC 604 processor", 0 },
- { "604e" , "Select the PowerPC 604e processor", 0 },
- { "620" , "Select the PowerPC 620 processor", 0 },
- { "7400" , "Select the PowerPC 7400 (G4) processor",
- PowerPCFeatureAltivec },
- { "7450" , "Select the PowerPC 7450 (G4+) processor",
- PowerPCFeatureAltivec },
- { "750" , "Select the PowerPC 750 (G3) processor", 0 },
- { "970" , "Select the PowerPC 970 (G5 - GPUL) processor",
- PowerPCFeature64Bit | PowerPCFeatureAltivec |
- PowerPCFeatureFSqrt | PowerPCFeatureGPUL },
- { "g3" , "Select the PowerPC G3 (750) processor", 0 },
- { "g4" , "Select the PowerPC G4 (7400) processor",
- PowerPCFeatureAltivec },
- { "g4+" , "Select the PowerPC G4+ (7450) processor",
- PowerPCFeatureAltivec },
- { "g5" , "Select the PowerPC g5 (970 - GPUL) processor",
- PowerPCFeature64Bit | PowerPCFeatureAltivec |
- PowerPCFeatureFSqrt | PowerPCFeatureGPUL },
- { "generic", "Select instructions for a generic PowerPC processor", 0 }
-};
-/// Length of PowerPCSubTypeKV.
-static const unsigned PowerPCSubTypeKVSize = sizeof(PowerPCSubTypeKV)
- / sizeof(SubtargetFeatureKV);
-
-/// Sorted (by key) array of values for CPU features.
-static SubtargetFeatureKV PowerPCFeatureKV[] = {
- { "64bit" , "Should 64 bit instructions be used" , PowerPCFeature64Bit },
- { "64bitregs", "Should 64 bit registers be used" , PowerPCFeature64BRegs },
- { "altivec", "Should Altivec instructions be used" , PowerPCFeatureAltivec },
- { "fsqrt" , "Should the fsqrt instruction be used", PowerPCFeatureFSqrt },
- { "gpul" , "Should GPUL instructions be used" , PowerPCFeatureGPUL }
- };
-/// Length of PowerPCFeatureKV.
-static const unsigned PowerPCFeatureKVSize = sizeof(PowerPCFeatureKV)
+}
+
+/// Length of FeatureKV.
+static const unsigned FeatureKVSize = sizeof(FeatureKV)
/ sizeof(SubtargetFeatureKV);
+/// Length of SubTypeKV.
+static const unsigned SubTypeKVSize = sizeof(SubTypeKV)
+ / sizeof(SubtargetFeatureKV);
#if defined(__APPLE__)
@@ -131,12 +87,11 @@
#endif
uint32_t Bits =
SubtargetFeatures::Parse(FS, CPU,
- PowerPCSubTypeKV, PowerPCSubTypeKVSize,
- PowerPCFeatureKV, PowerPCFeatureKVSize);
- IsGigaProcessor = (Bits & PowerPCFeatureGPUL ) != 0;
- Is64Bit = (Bits & PowerPCFeature64Bit) != 0;
- HasFSQRT = (Bits & PowerPCFeatureFSqrt) != 0;
- Has64BitRegs = (Bits & PowerPCFeature64BRegs) != 0;
+ SubTypeKV, SubTypeKVSize, FeatureKV, FeatureKVSize);
+ IsGigaProcessor = (Bits & FeatureGPUL ) != 0;
+ Is64Bit = (Bits & Feature64Bit) != 0;
+ HasFSQRT = (Bits & FeatureFSqrt) != 0;
+ Has64BitRegs = (Bits & Feature64BitRegs) != 0;
// Set the boolean corresponding to the current target triple, or the default
// if one cannot be determined, to true.
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