[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Nate Begeman]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.49 -> 1.50
---
Log message:

Fix a couple bugs in the const div stuff where we'd generate MULHS/MULHU
for types that aren't legal, and fail a divisor is less than zero
comparison, which would cause us to drop a subtract.


---
Diffs of the changes:  (+4 -3)

 DAGCombiner.cpp |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.49 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.50
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.49	Thu Oct 20 12:01:00 2005
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Thu Oct 20 12:45:03 2005
@@ -790,7 +790,8 @@
   // detect that too.
   if (N1C && !isPowerOf2_64(N1C->getSignExtended()) && 
       (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
-      TLI.isOperationLegal(ISD::MULHS, VT) && TLI.isIntDivExpensive()) {
+      TLI.isOperationLegal(ISD::MULHS, VT) && TLI.isTypeLegal(VT) &&
+      TLI.isIntDivExpensive()) {
     return BuildSDIV(N);
   }
   return SDOperand();
@@ -814,7 +815,7 @@
                                        TLI.getShiftAmountTy()));
   // fold (udiv x, c) -> alternate
   if (N1C && N1C->getValue() && TLI.isOperationLegal(ISD::MULHU, VT) &&
-      TLI.isIntDivExpensive())
+      TLI.isTypeLegal(VT) && TLI.isIntDivExpensive())
     return BuildUDIV(N);
   return SDOperand();
 }
@@ -2555,7 +2556,7 @@
   assert((VT == MVT::i32 || VT == MVT::i64) && 
          "BuildSDIV only operates on i32 or i64!");
   
-  int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
+  int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
   ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
   
   // Multiply the numerator (operand 0) by the magic value