[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC.td PPCInstrFormats.td PPCInstrInfo.td PPCSchedule.td PPCScheduleG3.td PPCScheduleG4.td PPCScheduleG4Plus.td PPCScheduleG5.td
Jim Laskey
jlaskey at apple.com
Wed Oct 19 12:51:28 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PPC.td updated: 1.2 -> 1.3
PPCInstrFormats.td updated: 1.53 -> 1.54
PPCInstrInfo.td updated: 1.129 -> 1.130
PPCSchedule.td updated: 1.2 -> 1.3
PPCScheduleG3.td updated: 1.3 -> 1.4
PPCScheduleG4.td updated: 1.3 -> 1.4
PPCScheduleG4Plus.td updated: 1.3 -> 1.4
PPCScheduleG5.td updated: 1.3 -> 1.4
---
Log message:
Added InstrSchedClass to each of the PowerPC Instructions.
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
---
Diffs of the changes: (+421 -386)
PPC.td | 37 +++++
PPCInstrFormats.td | 251 +++++++++++++++++++++----------------
PPCInstrInfo.td | 345 +++++++++++++++++++++++++--------------------------
PPCSchedule.td | 150 ++++++++--------------
PPCScheduleG3.td | 6
PPCScheduleG4.td | 6
PPCScheduleG4Plus.td | 6
PPCScheduleG5.td | 6
8 files changed, 421 insertions(+), 386 deletions(-)
Index: llvm/lib/Target/PowerPC/PPC.td
diff -u llvm/lib/Target/PowerPC/PPC.td:1.2 llvm/lib/Target/PowerPC/PPC.td:1.3
--- llvm/lib/Target/PowerPC/PPC.td:1.2 Fri Oct 14 18:40:39 2005
+++ llvm/lib/Target/PowerPC/PPC.td Wed Oct 19 14:51:16 2005
@@ -20,8 +20,45 @@
//===----------------------------------------------------------------------===//
include "PPCRegisterInfo.td"
+include "PPCSchedule.td"
include "PPCInstrInfo.td"
+
+
+//===----------------------------------------------------------------------===//
+// PowerPC Subtarget features.
+//
+
+def F64Bit : SubtargetFeature<"64bit",
+ "Should 64 bit instructions be used">;
+def F64BitRegs : SubtargetFeature<"64bitregs",
+ "Should 64 bit registers be used">;
+def FAltivec : SubtargetFeature<"altivec",
+ "Should Altivec instructions be used">;
+def FGPUL : SubtargetFeature<"gpul",
+ "Should GPUL instructions be used">;
+def FFSQRT : SubtargetFeature<"fsqrt",
+ "Should the fsqrt instruction be used">;
+
+//===----------------------------------------------------------------------===//
+// PowerPC chips sets supported
+//
+
+def : Processor<"601", G3Itineraries, []>;
+def : Processor<"602", G3Itineraries, []>;
+def : Processor<"603", G3Itineraries, []>;
+def : Processor<"604", G3Itineraries, []>;
+def : Processor<"750", G3Itineraries, []>;
+def : Processor<"7400", G4Itineraries, [FAltivec]>;
+def : Processor<"g4", G4Itineraries, [FAltivec]>;
+def : Processor<"7450", G4PlusItineraries, [FAltivec]>;
+def : Processor<"g4+", G4PlusItineraries, [FAltivec]>;
+def : Processor<"970", G5Itineraries,
+ [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;
+def : Processor<"g5", G5Itineraries,
+ [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;
+
+
def PPC : Target {
// Pointers on PPC are 32-bits in size.
let PointerType = i32;
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.53 llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.54
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.53 Wed Oct 19 13:42:01 2005
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Wed Oct 19 14:51:16 2005
@@ -14,7 +14,8 @@
//
// PowerPC instruction formats
-class I<bits<6> opcode, dag OL, string asmstr> : Instruction {
+class I<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
+ : Instruction {
field bits<32> Inst;
bit PPC64 = 0; // Default value, override with isPPC64
@@ -25,11 +26,13 @@
let Inst{0-5} = opcode;
let OperandList = OL;
let AsmString = asmstr;
+ let Itinerary = itin;
}
// 1.7.1 I-Form
-class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr>
- : I<opcode, OL, asmstr> {
+class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr,
+ InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<24> LI;
let Inst{6-29} = LI;
@@ -39,8 +42,8 @@
// 1.7.2 B-Form
class BForm<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<2> bicode, dag OL,
- string asmstr>
- : I<opcode, OL, asmstr> {
+ string asmstr, InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<3> CR;
bits<14> BD;
@@ -53,8 +56,9 @@
}
// 1.7.4 D-Form
-class DForm_base<bits<6> opcode, dag OL, string asmstr, list<dag> pattern>
- : I<opcode, OL, asmstr> {
+class DForm_base<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
+ list<dag> pattern>
+ : I<opcode, OL, asmstr, itin> {
let Pattern = pattern;
bits<5> A;
bits<5> B;
@@ -65,8 +69,8 @@
let Inst{16-31} = C;
}
-class DForm_1<bits<6> opcode, dag OL, string asmstr>
- : I<opcode, OL, asmstr> {
+class DForm_1<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<5> A;
bits<16> C;
bits<5> B;
@@ -76,11 +80,13 @@
let Inst{16-31} = C;
}
-class DForm_2<bits<6> opcode, dag OL, string asmstr, list<dag> pattern>
- : DForm_base<opcode, OL, asmstr, pattern>;
+class DForm_2<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
+ list<dag> pattern>
+ : DForm_base<opcode, OL, asmstr, itin, pattern>;
-class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, list<dag> pattern>
- : I<opcode, OL, asmstr> {
+class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
+ list<dag> pattern>
+ : I<opcode, OL, asmstr, itin> {
bits<5> A;
bits<16> B;
@@ -92,11 +98,12 @@
}
// Currently we make the use/def reg distinction in ISel, not tablegen
-class DForm_3<bits<6> opcode, dag OL, string asmstr>
- : DForm_1<opcode, OL, asmstr>;
+class DForm_3<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
+ : DForm_1<opcode, OL, asmstr, itin>;
-class DForm_4<bits<6> opcode, dag OL, string asmstr, list<dag> pattern>
- : I<opcode, OL, asmstr> {
+class DForm_4<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
+ list<dag> pattern>
+ : I<opcode, OL, asmstr, itin> {
bits<5> B;
bits<5> A;
bits<16> C;
@@ -108,14 +115,15 @@
let Inst{16-31} = C;
}
-class DForm_4_zero<bits<6> opcode, dag OL, string asmstr>
- : DForm_1<opcode, OL, asmstr> {
+class DForm_4_zero<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
+ : DForm_1<opcode, OL, asmstr, itin> {
let A = 0;
let B = 0;
let C = 0;
}
-class DForm_5<bits<6> opcode, dag OL, string asmstr> : I<opcode, OL, asmstr> {
+class DForm_5<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<3> BF;
bits<1> L;
bits<5> RA;
@@ -128,30 +136,31 @@
let Inst{16-31} = I;
}
-class DForm_5_ext<bits<6> opcode, dag OL, string asmstr>
- : DForm_5<opcode, OL, asmstr> {
+class DForm_5_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
+ : DForm_5<opcode, OL, asmstr, itin> {
let L = PPC64;
}
-class DForm_6<bits<6> opcode, dag OL, string asmstr>
- : DForm_5<opcode, OL, asmstr>;
+class DForm_6<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
+ : DForm_5<opcode, OL, asmstr, itin>;
-class DForm_6_ext<bits<6> opcode, dag OL, string asmstr>
- : DForm_6<opcode, OL, asmstr> {
+class DForm_6_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
+ : DForm_6<opcode, OL, asmstr, itin> {
let L = PPC64;
}
-class DForm_8<bits<6> opcode, dag OL, string asmstr>
- : DForm_1<opcode, OL, asmstr> {
+class DForm_8<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
+ : DForm_1<opcode, OL, asmstr, itin> {
}
-class DForm_9<bits<6> opcode, dag OL, string asmstr>
- : DForm_1<opcode, OL, asmstr> {
+class DForm_9<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
+ : DForm_1<opcode, OL, asmstr, itin> {
}
// 1.7.5 DS-Form
-class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr>
- : I<opcode, OL, asmstr> {
+class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<5> RST;
bits<14> DS;
bits<5> RA;
@@ -162,12 +171,14 @@
let Inst{30-31} = xo;
}
-class DSForm_2<bits<6> opcode, bits<2> xo, dag OL, string asmstr>
- : DSForm_1<opcode, xo, OL, asmstr>;
+class DSForm_2<bits<6> opcode, bits<2> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : DSForm_1<opcode, xo, OL, asmstr, itin>;
// 1.7.6 X-Form
class XForm_base_r3xo<bits<6> opcode, bits<10> xo,
- dag OL, string asmstr> : I<opcode, OL, asmstr> {
+ dag OL, string asmstr, InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<5> RST;
bits<5> A;
bits<5> B;
@@ -184,8 +195,9 @@
// This is the same as XForm_base_r3xo, but the first two operands are swapped
// when code is emitted.
class XForm_base_r3xo_swapped
- <bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : I<opcode, OL, asmstr> {
+ <bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<5> A;
bits<5> RST;
bits<5> B;
@@ -200,32 +212,36 @@
}
-class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : XForm_base_r3xo<opcode, xo, OL, asmstr>;
-
-class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
- list<dag> pattern>
- : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr> {
+class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : XForm_base_r3xo<opcode, xo, OL, asmstr, itin>;
+
+class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> {
let Pattern = pattern;
}
-class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : XForm_base_r3xo<opcode, xo, OL, asmstr>;
-
-class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr, list<dag> pt>
- : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr> {
- let Pattern = pt;
+class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : XForm_base_r3xo<opcode, xo, OL, asmstr, itin>;
+
+class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> {
+ let Pattern = pattern;
}
class XForm_11<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
- list<dag> pattern>
- : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr> {
+ InstrItinClass itin, list<dag> pattern>
+ : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> {
let B = 0;
let Pattern = pattern;
}
-class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : I<opcode, OL, asmstr> {
+class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<3> BF;
bits<1> L;
bits<5> RA;
@@ -240,13 +256,15 @@
let Inst{31} = 0;
}
-class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : XForm_16<opcode, xo, OL, asmstr> {
+class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : XForm_16<opcode, xo, OL, asmstr, itin> {
let L = PPC64;
}
-class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : I<opcode, OL, asmstr> {
+class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<3> BF;
bits<5> FRA;
bits<5> FRB;
@@ -259,23 +277,27 @@
let Inst{31} = 0;
}
-class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : XForm_base_r3xo<opcode, xo, OL, asmstr> {
+class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : XForm_base_r3xo<opcode, xo, OL, asmstr, itin> {
}
-class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr, list<dag> pt>
- : XForm_base_r3xo<opcode, xo, OL, asmstr> {
+class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : XForm_base_r3xo<opcode, xo, OL, asmstr, itin> {
let A = 0;
- let Pattern = pt;
+ let Pattern = pattern;
}
-class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : XForm_base_r3xo<opcode, xo, OL, asmstr> {
+class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : XForm_base_r3xo<opcode, xo, OL, asmstr, itin> {
}
// 1.7.7 XL-Form
-class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : I<opcode, OL, asmstr> {
+class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<3> CRD;
bits<2> CRDb;
bits<3> CRA;
@@ -293,8 +315,9 @@
let Inst{31} = 0;
}
-class XLForm_2<bits<6> opcode, bits<10> xo, bit lk,
- dag OL, string asmstr> : I<opcode, OL, asmstr> {
+class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OL, string asmstr,
+ InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<5> BO;
bits<5> BI;
bits<2> BH;
@@ -307,16 +330,17 @@
let Inst{31} = lk;
}
-class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo,
- bits<5> bi, bit lk, dag OL, string asmstr>
- : XLForm_2<opcode, xo, lk, OL, asmstr> {
+class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
+ dag OL, string asmstr, InstrItinClass itin>
+ : XLForm_2<opcode, xo, lk, OL, asmstr, itin> {
let BO = bo;
let BI = bi;
let BH = 0;
}
-class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : I<opcode, OL, asmstr> {
+class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<3> BF;
bits<3> BFA;
@@ -330,8 +354,9 @@
}
// 1.7.8 XFX-Form
-class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : I<opcode, OL, asmstr> {
+class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<5> RT;
bits<10> SPR;
@@ -342,13 +367,14 @@
}
class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
- dag OL, string asmstr>
- : XFXForm_1<opcode, xo, OL, asmstr> {
+ dag OL, string asmstr, InstrItinClass itin>
+ : XFXForm_1<opcode, xo, OL, asmstr, itin> {
let SPR = spr;
}
-class XFXForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : I<opcode, OL, asmstr> {
+class XFXForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<5> RT;
let Inst{6-10} = RT;
@@ -357,8 +383,9 @@
let Inst{31} = 0;
}
-class XFXForm_5<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : I<opcode, OL, asmstr> {
+class XFXForm_5<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<8> FXM;
bits<5> ST;
@@ -370,8 +397,9 @@
let Inst{31} = 0;
}
-class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : I<opcode, OL, asmstr> {
+class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<5> ST;
bits<8> FXM;
@@ -384,18 +412,20 @@
}
-class XFXForm_7<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : XFXForm_1<opcode, xo, OL, asmstr>;
+class XFXForm_7<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : XFXForm_1<opcode, xo, OL, asmstr, itin>;
class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
- dag OL, string asmstr>
- : XFXForm_7<opcode, xo, OL, asmstr> {
+ dag OL, string asmstr, InstrItinClass itin>
+ : XFXForm_7<opcode, xo, OL, asmstr, itin> {
let SPR = spr;
}
// 1.7.10 XS-Form
-class XSForm_1<bits<6> opcode, bits<9> xo, dag OL, string asmstr>
- : I<opcode, OL, asmstr> {
+class XSForm_1<bits<6> opcode, bits<9> xo, dag OL, string asmstr,
+ InstrItinClass itin>
+ : I<opcode, OL, asmstr, itin> {
bits<5> RS;
bits<5> A;
bits<6> SH;
@@ -412,8 +442,8 @@
// 1.7.11 XO-Form
class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OL, string asmstr,
- list<dag> pattern>
- : I<opcode, OL, asmstr> {
+ InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OL, asmstr, itin> {
bits<5> RT;
bits<5> RA;
bits<5> RB;
@@ -431,15 +461,15 @@
}
class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
- dag OL, string asmstr, list<dag> pattern>
- : XOForm_1<opcode, xo, oe, OL, asmstr, pattern> {
+ dag OL, string asmstr, InstrItinClass itin, list<dag> pattern>
+ : XOForm_1<opcode, xo, oe, OL, asmstr, itin, pattern> {
let RB = 0;
}
// 1.7.12 A-Form
class AForm_1<bits<6> opcode, bits<5> xo, dag OL, string asmstr,
- list<dag> pattern>
- : I<opcode, OL, asmstr> {
+ InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OL, asmstr, itin> {
bits<5> FRT;
bits<5> FRA;
bits<5> FRC;
@@ -457,19 +487,22 @@
let Inst{31} = RC;
}
-class AForm_2<bits<6> opcode, bits<5> xo, dag OL, string asmstr, list<dag> pat>
- : AForm_1<opcode, xo, OL, asmstr, pat> {
+class AForm_2<bits<6> opcode, bits<5> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : AForm_1<opcode, xo, OL, asmstr, itin, pattern> {
let FRC = 0;
}
-class AForm_3<bits<6> opcode, bits<5> xo, dag OL, string asmstr, list<dag> pat>
- : AForm_1<opcode, xo, OL, asmstr, pat> {
+class AForm_3<bits<6> opcode, bits<5> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : AForm_1<opcode, xo, OL, asmstr, itin, pattern> {
let FRB = 0;
}
// 1.7.13 M-Form
-class MForm_1<bits<6> opcode, dag OL, string asmstr, list<dag> pattern>
- : I<opcode, OL, asmstr> {
+class MForm_1<bits<6> opcode, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OL, asmstr, itin> {
bits<5> RA;
bits<5> RS;
bits<5> RB;
@@ -488,14 +521,15 @@
let Inst{31} = RC;
}
-class MForm_2<bits<6> opcode, dag OL, string asmstr, list<dag> pattern>
- : MForm_1<opcode, OL, asmstr, pattern> {
+class MForm_2<bits<6> opcode, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : MForm_1<opcode, OL, asmstr, itin, pattern> {
}
// 1.7.14 MD-Form
-class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr,
- list<dag> pattern>
- : I<opcode, OL, asmstr> {
+class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OL, asmstr, itin> {
bits<5> RS;
bits<5> RA;
bits<6> SH;
@@ -515,8 +549,9 @@
}
//===----------------------------------------------------------------------===//
-
-class Pseudo<dag OL, string asmstr> : I<0, OL, asmstr> {
+def NoItin : InstrItinClass;
+class Pseudo<dag OL, string asmstr>
+ : I<0, OL, asmstr, NoItin> {
let PPC64 = 0;
let VMX = 0;
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.129 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.130
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.129 Wed Oct 19 13:42:01 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Wed Oct 19 14:51:16 2005
@@ -159,8 +159,8 @@
let isTerminator = 1 in {
let isReturn = 1 in
- def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
- def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
+ def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB>;
+ def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB>;
}
let Defs = [LR] in
@@ -170,25 +170,25 @@
def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
target:$true, target:$false),
"; COND_BRANCH">;
- def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
-//def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
- def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
-//def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
+ def B : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>;
+//def BA : IForm<18, 1, 0, (ops target:$func), "ba $func", BrB>;
+ def BL : IForm<18, 0, 1, (ops target:$func), "bl $func", BrB>;
+//def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func", BrB>;
// FIXME: 4*CR# needs to be added to the BI field!
// This will only work for CR0 as it stands now
def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
- "blt $crS, $block">;
+ "blt $crS, $block", BrB>;
def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
- "ble $crS, $block">;
+ "ble $crS, $block", BrB>;
def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
- "beq $crS, $block">;
+ "beq $crS, $block", BrB>;
def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
- "bge $crS, $block">;
+ "bge $crS, $block", BrB>;
def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
- "bgt $crS, $block">;
+ "bgt $crS, $block", BrB>;
def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
- "bne $crS, $block">;
+ "bne $crS, $block", BrB>;
}
let isCall = 1,
@@ -198,9 +198,10 @@
LR,CTR,
CR0,CR1,CR5,CR6,CR7] in {
// Convenient aliases for call instructions
- def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">;
+ def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops),
+ "bl $func", BrB>;
def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
- (ops variable_ops), "bctrl">;
+ (ops variable_ops), "bctrl", BrB>;
}
// D-Form instructions. Most instructions that perform an operation on a
@@ -208,114 +209,114 @@
//
let isLoad = 1 in {
def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
- "lbz $rD, $disp($rA)">;
+ "lbz $rD, $disp($rA)", LdStGeneral>;
def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
- "lha $rD, $disp($rA)">;
+ "lha $rD, $disp($rA)", LdStLHA>;
def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
- "lhz $rD, $disp($rA)">;
+ "lhz $rD, $disp($rA)", LdStGeneral>;
def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
- "lmw $rD, $disp($rA)">;
+ "lmw $rD, $disp($rA)", LdStLMW>;
def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
- "lwz $rD, $disp($rA)">;
+ "lwz $rD, $disp($rA)", LdStGeneral>;
def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
- "lwzu $rD, $disp($rA)">;
+ "lwzu $rD, $disp($rA)", LdStGeneral>;
}
def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
- "addi $rD, $rA, $imm",
+ "addi $rD, $rA, $imm", IntGeneral,
[(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
- "addic $rD, $rA, $imm",
+ "addic $rD, $rA, $imm", IntGeneral,
[]>;
def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
- "addic. $rD, $rA, $imm",
+ "addic. $rD, $rA, $imm", IntGeneral,
[]>;
def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
- "addis $rD, $rA, $imm",
+ "addis $rD, $rA, $imm", IntGeneral,
[(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
- "la $rD, $sym($rA)",
+ "la $rD, $sym($rA)", IntGeneral,
[]>;
def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
- "mulli $rD, $rA, $imm",
+ "mulli $rD, $rA, $imm", IntMulLI,
[(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
- "subfic $rD, $rA, $imm",
+ "subfic $rD, $rA, $imm", IntGeneral,
[(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
- "li $rD, $imm",
+ "li $rD, $imm", IntGeneral,
[(set GPRC:$rD, immSExt16:$imm)]>;
def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
- "lis $rD, $imm",
+ "lis $rD, $imm", IntGeneral,
[(set GPRC:$rD, imm16Shifted:$imm)]>;
let isStore = 1 in {
def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
- "stmw $rS, $disp($rA)">;
+ "stmw $rS, $disp($rA)", LdStLMW>;
def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
- "stb $rS, $disp($rA)">;
+ "stb $rS, $disp($rA)", LdStGeneral>;
def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
- "sth $rS, $disp($rA)">;
+ "sth $rS, $disp($rA)", LdStGeneral>;
def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
- "stw $rS, $disp($rA)">;
+ "stw $rS, $disp($rA)", LdStGeneral>;
def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
- "stwu $rS, $disp($rA)">;
+ "stwu $rS, $disp($rA)", LdStGeneral>;
}
def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "andi. $dst, $src1, $src2",
+ "andi. $dst, $src1, $src2", IntGeneral,
[]>, isDOT;
def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "andis. $dst, $src1, $src2",
+ "andis. $dst, $src1, $src2", IntGeneral,
[]>, isDOT;
def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "ori $dst, $src1, $src2",
+ "ori $dst, $src1, $src2", IntGeneral,
[(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "oris $dst, $src1, $src2",
+ "oris $dst, $src1, $src2", IntGeneral,
[(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "xori $dst, $src1, $src2",
+ "xori $dst, $src1, $src2", IntGeneral,
[(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
- "xoris $dst, $src1, $src2",
+ "xoris $dst, $src1, $src2", IntGeneral,
[(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
-def NOP : DForm_4_zero<24, (ops), "nop">;
+def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral>;
def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
- "cmpi $crD, $L, $rA, $imm">;
+ "cmpi $crD, $L, $rA, $imm", IntCompare>;
def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
- "cmpwi $crD, $rA, $imm">;
+ "cmpwi $crD, $rA, $imm", IntCompare>;
def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
- "cmpdi $crD, $rA, $imm">, isPPC64;
+ "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
- "cmpli $dst, $size, $src1, $src2">;
+ "cmpli $dst, $size, $src1, $src2", IntCompare>;
def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
- "cmplwi $dst, $src1, $src2">;
+ "cmplwi $dst, $src1, $src2", IntCompare>;
def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
- "cmpldi $dst, $src1, $src2">, isPPC64;
+ "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
let isLoad = 1 in {
def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
- "lfs $rD, $disp($rA)">;
+ "lfs $rD, $disp($rA)", LdStLFDU>;
def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
- "lfd $rD, $disp($rA)">;
+ "lfd $rD, $disp($rA)", LdStLFD>;
}
let isStore = 1 in {
def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
- "stfs $rS, $disp($rA)">;
+ "stfs $rS, $disp($rA)", LdStUX>;
def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
- "stfd $rS, $disp($rA)">;
+ "stfd $rS, $disp($rA)", LdStUX>;
}
// DS-Form instructions. Load/Store instructions available in PPC-64
//
let isLoad = 1 in {
def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
- "lwa $rT, $DS($rA)">, isPPC64;
+ "lwa $rT, $DS($rA)", LdStLWA>, isPPC64;
def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
- "ld $rT, $DS($rA)">, isPPC64;
+ "ld $rT, $DS($rA)", LdStLD>, isPPC64;
}
let isStore = 1 in {
def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
- "std $rT, $DS($rA)">, isPPC64;
+ "std $rT, $DS($rA)", LdStSTD>, isPPC64;
def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
- "stdu $rT, $DS($rA)">, isPPC64;
+ "stdu $rT, $DS($rA)", LdStSTD>, isPPC64;
}
// X-Form instructions. Most instructions that perform an operation on a
@@ -323,270 +324,270 @@
//
let isLoad = 1 in {
def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
- "lbzx $dst, $base, $index">;
+ "lbzx $dst, $base, $index", LdStGeneral>;
def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
- "lhax $dst, $base, $index">;
+ "lhax $dst, $base, $index", LdStLHA>;
def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
- "lhzx $dst, $base, $index">;
+ "lhzx $dst, $base, $index", LdStGeneral>;
def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
- "lwax $dst, $base, $index">, isPPC64;
+ "lwax $dst, $base, $index", LdStLHA>, isPPC64;
def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
- "lwzx $dst, $base, $index">;
+ "lwzx $dst, $base, $index", LdStGeneral>;
def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
- "ldx $dst, $base, $index">, isPPC64;
+ "ldx $dst, $base, $index", LdStLD>, isPPC64;
}
def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "nand $rA, $rS, $rB",
+ "nand $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "and $rA, $rS, $rB",
+ "and $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "and. $rA, $rS, $rB",
+ "and. $rA, $rS, $rB", IntGeneral,
[]>, isDOT;
def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "andc $rA, $rS, $rB",
+ "andc $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "or $rA, $rS, $rB",
+ "or $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
- "or $rA, $rS, $rB",
+ "or $rA, $rS, $rB", IntGeneral,
[(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
- "or $rA, $rS, $rB",
+ "or $rA, $rS, $rB", IntGeneral,
[]>;
def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
- "or $rA, $rS, $rB",
+ "or $rA, $rS, $rB", IntGeneral,
[]>;
def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "nor $rA, $rS, $rB",
+ "nor $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "or. $rA, $rS, $rB",
+ "or. $rA, $rS, $rB", IntGeneral,
[]>, isDOT;
def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "orc $rA, $rS, $rB",
+ "orc $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "eqv $rA, $rS, $rB",
+ "eqv $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "xor $rA, $rS, $rB",
+ "xor $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
- "sld $rA, $rS, $rB",
+ "sld $rA, $rS, $rB", IntRotateD,
[(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "slw $rA, $rS, $rB",
+ "slw $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
- "srd $rA, $rS, $rB",
+ "srd $rA, $rS, $rB", IntRotateD,
[(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "srw $rA, $rS, $rB",
+ "srw $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
- "srad $rA, $rS, $rB",
+ "srad $rA, $rS, $rB", IntRotateD,
[(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "sraw $rA, $rS, $rB",
+ "sraw $rA, $rS, $rB", IntShift,
[(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
let isStore = 1 in {
def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- "stbx $rS, $rA, $rB">;
+ "stbx $rS, $rA, $rB", LdStGeneral>;
def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- "sthx $rS, $rA, $rB">;
+ "sthx $rS, $rA, $rB", LdStGeneral>;
def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- "stwx $rS, $rA, $rB">;
+ "stwx $rS, $rA, $rB", LdStGeneral>;
def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- "stwux $rS, $rA, $rB">;
+ "stwux $rS, $rA, $rB", LdStGeneral>;
def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- "stdx $rS, $rA, $rB">, isPPC64;
+ "stdx $rS, $rA, $rB", LdStSTD>, isPPC64;
def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- "stdux $rS, $rA, $rB">, isPPC64;
+ "stdux $rS, $rA, $rB", LdStSTD>, isPPC64;
}
def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
- "srawi $rA, $rS, $SH",
+ "srawi $rA, $rS, $SH", IntShift,
[(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
- "cntlzw $rA, $rS",
+ "cntlzw $rA, $rS", IntGeneral,
[(set GPRC:$rA, (ctlz GPRC:$rS))]>;
def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
- "extsb $rA, $rS",
+ "extsb $rA, $rS", IntGeneral,
[(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
- "extsh $rA, $rS",
+ "extsh $rA, $rS", IntGeneral,
[(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
- "extsw $rA, $rS",
+ "extsw $rA, $rS", IntRotateD,
[]>, isPPC64;
def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
- "cmp $crD, $long, $rA, $rB">;
+ "cmp $crD, $long, $rA, $rB", IntCompare>;
def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
- "cmpl $crD, $long, $rA, $rB">;
+ "cmpl $crD, $long, $rA, $rB", IntCompare>;
def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
- "cmpw $crD, $rA, $rB">;
+ "cmpw $crD, $rA, $rB", IntCompare>;
def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
- "cmpd $crD, $rA, $rB">, isPPC64;
+ "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
- "cmplw $crD, $rA, $rB">;
+ "cmplw $crD, $rA, $rB", IntCompare>;
def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
- "cmpld $crD, $rA, $rB">, isPPC64;
+ "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
//def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
-// "fcmpo $crD, $fA, $fB">;
+// "fcmpo $crD, $fA, $fB", FPCompare>;
def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
- "fcmpu $crD, $fA, $fB">;
+ "fcmpu $crD, $fA, $fB", FPCompare>;
def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
- "fcmpu $crD, $fA, $fB">;
+ "fcmpu $crD, $fA, $fB", FPCompare>;
let isLoad = 1 in {
def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
- "lfsx $dst, $base, $index">;
+ "lfsx $dst, $base, $index", LdStLFDU>;
def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
- "lfdx $dst, $base, $index">;
+ "lfdx $dst, $base, $index", LdStLFDU>;
}
def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
- "fcfid $frD, $frB",
+ "fcfid $frD, $frB", FPGeneral,
[]>, isPPC64;
def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
- "fctidz $frD, $frB",
+ "fctidz $frD, $frB", FPGeneral,
[]>, isPPC64;
def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
- "fctiwz $frD, $frB",
+ "fctiwz $frD, $frB", FPGeneral,
[]>;
def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
- "frsp $frD, $frB",
+ "frsp $frD, $frB", FPGeneral,
[(set F4RC:$frD, (fround F8RC:$frB))]>;
def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
- "fsqrt $frD, $frB",
+ "fsqrt $frD, $frB", FPSqrt,
[(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
- "fsqrts $frD, $frB",
+ "fsqrts $frD, $frB", FPSqrt,
[(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
- "fmr $frD, $frB",
+ "fmr $frD, $frB", FPGeneral,
[]>; // (set F4RC:$frD, F4RC:$frB)
def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
- "fmr $frD, $frB",
+ "fmr $frD, $frB", FPGeneral,
[]>; // (set F8RC:$frD, F8RC:$frB)
def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
- "fmr $frD, $frB",
+ "fmr $frD, $frB", FPGeneral,
[(set F8RC:$frD, (fextend F4RC:$frB))]>;
// These are artificially split into two different forms, for 4/8 byte FP.
def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
- "fabs $frD, $frB",
+ "fabs $frD, $frB", FPGeneral,
[(set F4RC:$frD, (fabs F4RC:$frB))]>;
def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
- "fabs $frD, $frB",
+ "fabs $frD, $frB", FPGeneral,
[(set F8RC:$frD, (fabs F8RC:$frB))]>;
def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
- "fnabs $frD, $frB",
+ "fnabs $frD, $frB", FPGeneral,
[(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
- "fnabs $frD, $frB",
+ "fnabs $frD, $frB", FPGeneral,
[(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
- "fneg $frD, $frB",
+ "fneg $frD, $frB", FPGeneral,
[(set F4RC:$frD, (fneg F4RC:$frB))]>;
def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
- "fneg $frD, $frB",
+ "fneg $frD, $frB", FPGeneral,
[(set F8RC:$frD, (fneg F8RC:$frB))]>;
let isStore = 1 in {
def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
- "stfsx $frS, $rA, $rB">;
+ "stfsx $frS, $rA, $rB", LdStUX>;
def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
- "stfdx $frS, $rA, $rB">;
+ "stfdx $frS, $rA, $rB", LdStUX>;
}
// XL-Form instructions. condition register logical ops.
//
def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
- "mcrf $BF, $BFA">;
+ "mcrf $BF, $BFA", BrMCR>;
// XFX-Form instructions. Instructions that deal with SPRs
//
// Note that although LR should be listed as `8' and CTR as `9' in the SPR
// field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
// which means the SPR value needs to be multiplied by a factor of 32.
-def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
-def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
-def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
+def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
+def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
+def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
- "mtcrf $FXM, $rS">;
+ "mtcrf $FXM, $rS", BrMCRX>;
def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
- "mfcr $rT, $FXM">;
-def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
-def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
+ "mfcr $rT, $FXM", SprMFCR>;
+def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
+def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
// XS-Form instructions. Just 'sradi'
//
def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
- "sradi $rA, $rS, $SH">, isPPC64;
+ "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
// XO-Form instructions. Arithmetic instructions that can set overflow bit
//
def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "add $rT, $rA, $rB",
+ "add $rT, $rA, $rB", IntGeneral,
[(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
- "add $rT, $rA, $rB",
+ "add $rT, $rA, $rB", IntGeneral,
[(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "addc $rT, $rA, $rB",
+ "addc $rT, $rA, $rB", IntGeneral,
[]>;
def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "adde $rT, $rA, $rB",
+ "adde $rT, $rA, $rB", IntGeneral,
[]>;
def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "divd $rT, $rA, $rB",
+ "divd $rT, $rA, $rB", IntDivD,
[]>, isPPC64;
def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "divdu $rT, $rA, $rB",
+ "divdu $rT, $rA, $rB", IntDivD,
[]>, isPPC64;
def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "divw $rT, $rA, $rB",
+ "divw $rT, $rA, $rB", IntDivW,
[(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "divwu $rT, $rA, $rB",
+ "divwu $rT, $rA, $rB", IntDivW,
[(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "mulhw $rT, $rA, $rB",
+ "mulhw $rT, $rA, $rB", IntMulHW,
[(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "mulhwu $rT, $rA, $rB",
+ "mulhwu $rT, $rA, $rB", IntMulHWU,
[(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "mulld $rT, $rA, $rB",
+ "mulld $rT, $rA, $rB", IntMulHD,
[]>, isPPC64;
def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "mullw $rT, $rA, $rB",
+ "mullw $rT, $rA, $rB", IntMulHW,
[(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "subf $rT, $rA, $rB",
+ "subf $rT, $rA, $rB", IntGeneral,
[(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "subfc $rT, $rA, $rB",
+ "subfc $rT, $rA, $rB", IntGeneral,
[]>;
def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "subfe $rT, $rA, $rB",
+ "subfe $rT, $rA, $rB", IntGeneral,
[]>;
def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
- "addme $rT, $rA",
+ "addme $rT, $rA", IntGeneral,
[]>;
def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
- "addze $rT, $rA",
+ "addze $rT, $rA", IntGeneral,
[]>;
def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
- "neg $rT, $rA",
+ "neg $rT, $rA", IntGeneral,
[(set GPRC:$rT, (ineg GPRC:$rA))]>;
def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
- "subfze $rT, $rA",
+ "subfze $rT, $rA", IntGeneral,
[]>;
// A-Form instructions. Most of the instructions executed in the FPU are of
@@ -594,42 +595,42 @@
//
def FMADD : AForm_1<63, 29,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
- "fmadd $FRT, $FRA, $FRC, $FRB",
+ "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
[(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
F8RC:$FRB))]>;
def FMADDS : AForm_1<59, 29,
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
- "fmadds $FRT, $FRA, $FRC, $FRB",
+ "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
[(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
F4RC:$FRB))]>;
def FMSUB : AForm_1<63, 28,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
- "fmsub $FRT, $FRA, $FRC, $FRB",
+ "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
[(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
F8RC:$FRB))]>;
def FMSUBS : AForm_1<59, 28,
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
- "fmsubs $FRT, $FRA, $FRC, $FRB",
+ "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
[(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
F4RC:$FRB))]>;
def FNMADD : AForm_1<63, 31,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
- "fnmadd $FRT, $FRA, $FRC, $FRB",
+ "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
[(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
F8RC:$FRB)))]>;
def FNMADDS : AForm_1<59, 31,
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
- "fnmadds $FRT, $FRA, $FRC, $FRB",
+ "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
[(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
F4RC:$FRB)))]>;
def FNMSUB : AForm_1<63, 30,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
- "fnmsub $FRT, $FRA, $FRC, $FRB",
+ "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
[(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
F8RC:$FRB)))]>;
def FNMSUBS : AForm_1<59, 30,
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
- "fnmsubs $FRT, $FRA, $FRC, $FRB",
+ "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
[(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
F4RC:$FRB)))]>;
// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
@@ -638,43 +639,43 @@
// and 4/8 byte forms for the result and operand type..
def FSELD : AForm_1<63, 23,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
- "fsel $FRT, $FRA, $FRC, $FRB",
+ "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
[]>;
def FSELS : AForm_1<63, 23,
(ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
- "fsel $FRT, $FRA, $FRC, $FRB",
+ "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
[]>;
def FADD : AForm_2<63, 21,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
- "fadd $FRT, $FRA, $FRB",
+ "fadd $FRT, $FRA, $FRB", FPGeneral,
[(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
def FADDS : AForm_2<59, 21,
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
- "fadds $FRT, $FRA, $FRB",
+ "fadds $FRT, $FRA, $FRB", FPGeneral,
[(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
def FDIV : AForm_2<63, 18,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
- "fdiv $FRT, $FRA, $FRB",
+ "fdiv $FRT, $FRA, $FRB", FPDivD,
[(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
def FDIVS : AForm_2<59, 18,
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
- "fdivs $FRT, $FRA, $FRB",
+ "fdivs $FRT, $FRA, $FRB", FPDivS,
[(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
def FMUL : AForm_3<63, 25,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
- "fmul $FRT, $FRA, $FRB",
+ "fmul $FRT, $FRA, $FRB", FPFused,
[(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
def FMULS : AForm_3<59, 25,
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
- "fmuls $FRT, $FRA, $FRB",
+ "fmuls $FRT, $FRA, $FRB", FPGeneral,
[(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
def FSUB : AForm_2<63, 20,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
- "fsub $FRT, $FRA, $FRB",
+ "fsub $FRT, $FRA, $FRB", FPGeneral,
[(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
def FSUBS : AForm_2<59, 20,
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
- "fsubs $FRT, $FRA, $FRB",
+ "fsubs $FRT, $FRA, $FRB", FPGeneral,
[(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
// M-Form instructions. rotate and mask instructions.
@@ -683,35 +684,35 @@
// RLWIMI can be commuted if the rotate amount is zero.
def RLWIMI : MForm_2<20,
(ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
- u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME",
+ u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
[]>;
def RLDIMI : MDForm_1<30, 3,
(ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
- "rldimi $rA, $rS, $SH, $MB",
+ "rldimi $rA, $rS, $SH, $MB", IntRotateD,
[]>, isPPC64;
}
def RLWINM : MForm_2<21,
(ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
- "rlwinm $rA, $rS, $SH, $MB, $ME",
+ "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
[]>;
def RLWINMo : MForm_2<21,
(ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
- "rlwinm. $rA, $rS, $SH, $MB, $ME",
+ "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
[]>, isDOT;
def RLWNM : MForm_2<23,
(ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
- "rlwnm $rA, $rS, $rB, $MB, $ME",
+ "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
[]>;
// MD-Form instructions. 64 bit rotate instructions.
//
def RLDICL : MDForm_1<30, 0,
(ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
- "rldicl $rA, $rS, $SH, $MB",
+ "rldicl $rA, $rS, $SH, $MB", IntRotateD,
[]>, isPPC64;
def RLDICR : MDForm_1<30, 1,
(ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
- "rldicr $rA, $rS, $SH, $ME",
+ "rldicr $rA, $rS, $SH, $ME", IntRotateD,
[]>, isPPC64;
//===----------------------------------------------------------------------===//
Index: llvm/lib/Target/PowerPC/PPCSchedule.td
diff -u llvm/lib/Target/PowerPC/PPCSchedule.td:1.2 llvm/lib/Target/PowerPC/PPCSchedule.td:1.3
--- llvm/lib/Target/PowerPC/PPCSchedule.td:1.2 Wed Oct 19 08:34:52 2005
+++ llvm/lib/Target/PowerPC/PPCSchedule.td Wed Oct 19 14:51:16 2005
@@ -7,8 +7,6 @@
//
//===----------------------------------------------------------------------===//
-#include "../Target.td"
-
//===----------------------------------------------------------------------===//
// Functional units across PowerPC chips sets
//
@@ -55,17 +53,17 @@
def LdStDCBA : InstrItinClass;
def LdStDCBF : InstrItinClass;
def LdStDCBI : InstrItinClass;
-def LdStDCBT : InstrItinClass;
+def LdStGeneral : InstrItinClass;
def LdStDSS : InstrItinClass;
def LdStICBI : InstrItinClass;
-def LdStLBZUX : InstrItinClass;
+def LdStUX : InstrItinClass;
def LdStLD : InstrItinClass;
def LdStLDARX : InstrItinClass;
def LdStLFD : InstrItinClass;
def LdStLFDU : InstrItinClass;
def LdStLHA : InstrItinClass;
def LdStLMW : InstrItinClass;
-def LdStLVEBX : InstrItinClass;
+def LdStLVecX : InstrItinClass;
def LdStLWA : InstrItinClass;
def LdStLWARX : InstrItinClass;
def LdStSLBIA : InstrItinClass;
@@ -107,10 +105,10 @@
//===----------------------------------------------------------------------===//
// Processor instruction itineraries.
-#include "PPCScheduleG3.td"
-#include "PPCScheduleG4.td"
-#include "PPCScheduleG4Plus.td"
-#include "PPCScheduleG5.td"
+include "PPCScheduleG3.td"
+include "PPCScheduleG4.td"
+include "PPCScheduleG4Plus.td"
+include "PPCScheduleG5.td"
//===----------------------------------------------------------------------===//
// Instruction to itinerary class map - When add new opcodes to the supported
@@ -154,8 +152,8 @@
// dcbf LdStDCBF
// dcbi LdStDCBI
// dcbst LdStDCBF
-// dcbt LdStDCBT
-// dcbtst LdStDCBT
+// dcbt LdStGeneral
+// dcbtst LdStGeneral
// dcbz LdStDCBF
// divd IntDivD
// divdu IntDivD
@@ -164,9 +162,9 @@
// dss LdStDSS
// dst LdStDSS
// dstst LdStDSS
-// eciwx LdStDCBT
-// ecowx LdStDCBT
-// eieio LdStDCBT
+// eciwx LdStGeneral
+// ecowx LdStGeneral
+// eieio LdStGeneral
// eqv IntGeneral
// extsb IntGeneral
// extsh IntGeneral
@@ -206,10 +204,10 @@
// fsubs FPGeneral
// icbi LdStICBI
// isync SprISYNC
-// lbz LdStDCBT
-// lbzu LdStDCBT
-// lbzux LdStLBZUX
-// lbzx LdStDCBT
+// lbz LdStGeneral
+// lbzu LdStGeneral
+// lbzux LdStUX
+// lbzx LdStGeneral
// ld LdStLD
// ldarx LdStLDARX
// ldu LdStLD
@@ -227,30 +225,30 @@
// lhau LdStLHA
// lhaux LdStLHA
// lhax LdStLHA
-// lhbrx LdStDCBT
-// lhz LdStDCBT
-// lhzu LdStDCBT
-// lhzux LdStLBZUX
-// lhzx LdStDCBT
+// lhbrx LdStGeneral
+// lhz LdStGeneral
+// lhzu LdStGeneral
+// lhzux LdStUX
+// lhzx LdStGeneral
// lmw LdStLMW
// lswi LdStLMW
// lswx LdStLMW
-// lvebx LdStLVEBX
-// lvehx LdStLVEBX
-// lvewx LdStLVEBX
-// lvsl LdStLVEBX
-// lvsr LdStLVEBX
-// lvx LdStLVEBX
-// lvxl LdStLVEBX
+// lvebx LdStLVecX
+// lvehx LdStLVecX
+// lvewx LdStLVecX
+// lvsl LdStLVecX
+// lvsr LdStLVecX
+// lvx LdStLVecX
+// lvxl LdStLVecX
// lwa LdStLWA
// lwarx LdStLWARX
// lwaux LdStLHA
// lwax LdStLHA
-// lwbrx LdStDCBT
-// lwz LdStDCBT
-// lwzu LdStDCBT
-// lwzux LdStLBZUX
-// lwzx LdStDCBT
+// lwbrx LdStGeneral
+// lwz LdStGeneral
+// lwzu LdStGeneral
+// lwzux LdStUX
+// lwzx LdStGeneral
// mcrf BrMCR
// mcrfs FPGeneral
// mcrxr BrMCRX
@@ -311,29 +309,29 @@
// srawi IntShift
// srd IntRotateD
// srw IntGeneral
-// stb LdStDCBT
-// stbu LdStDCBT
-// stbux LdStDCBT
-// stbx LdStDCBT
+// stb LdStGeneral
+// stbu LdStGeneral
+// stbux LdStGeneral
+// stbx LdStGeneral
// std LdStSTD
// stdcx. LdStSTDCX
// stdu LdStSTD
// stdux LdStSTD
// stdx LdStSTD
-// stfd LdStLBZUX
-// stfdu LdStLBZUX
-// stfdux LdStLBZUX
-// stfdx LdStLBZUX
-// stfiwx LdStLBZUX
-// stfs LdStLBZUX
-// stfsu LdStLBZUX
-// stfsux LdStLBZUX
-// stfsx LdStLBZUX
-// sth LdStDCBT
-// sthbrx LdStDCBT
-// sthu LdStDCBT
-// sthux LdStDCBT
-// sthx LdStDCBT
+// stfd LdStUX
+// stfdu LdStUX
+// stfdux LdStUX
+// stfdx LdStUX
+// stfiwx LdStUX
+// stfs LdStUX
+// stfsu LdStUX
+// stfsux LdStUX
+// stfsx LdStUX
+// sth LdStGeneral
+// sthbrx LdStGeneral
+// sthu LdStGeneral
+// sthux LdStGeneral
+// sthx LdStGeneral
// stmw LdStLMW
// stswi LdStLMW
// stswx LdStLMW
@@ -342,12 +340,12 @@
// stvewx LdStSTVEBX
// stvx LdStSTVEBX
// stvxl LdStSTVEBX
-// stw LdStDCBT
-// stwbrx LdStDCBT
+// stw LdStGeneral
+// stwbrx LdStGeneral
// stwcx. LdStSTWCX
-// stwu LdStDCBT
-// stwux LdStDCBT
-// stwx LdStDCBT
+// stwu LdStGeneral
+// stwux LdStGeneral
+// stwx LdStGeneral
// subf IntGeneral
// subfc IntGeneral
// subfe IntGeneral
@@ -508,39 +506,3 @@
// xori IntGeneral
// xoris IntGeneral
//
-
-
-//===----------------------------------------------------------------------===//
-// PowerPC Subtarget features.
-//
-
-def F64Bit : SubtargetFeature<"64bit",
- "Should 64 bit instructions be used">;
-def F64BitRegs : SubtargetFeature<"64bitregs",
- "Should 64 bit registers be used">;
-def FAltivec : SubtargetFeature<"altivec",
- "Should Altivec instructions be used">;
-def FGPUL : SubtargetFeature<"gpul",
- "Should GPUL instructions be used">;
-def FFSQRT : SubtargetFeature<"fsqrt",
- "Should the fsqrt instruction be used">;
-
-//===----------------------------------------------------------------------===//
-// PowerPC chips sets supported
-//
-
-def : Processor<"601", G3Itineraries, []>;
-def : Processor<"602", G3Itineraries, []>;
-def : Processor<"603", G3Itineraries, []>;
-def : Processor<"604", G3Itineraries, []>;
-def : Processor<"750", G3Itineraries, []>;
-def : Processor<"7400", G4Itineraries, [FAltivec]>;
-def : Processor<"g4", G4Itineraries, [FAltivec]>;
-def : Processor<"7450", G4PlusItineraries, [FAltivec]>;
-def : Processor<"g4+", G4PlusItineraries, [FAltivec]>;
-def : Processor<"970", G5Itineraries,
- [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;
-def : Processor<"g5", G5Itineraries,
- [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;
-
-
Index: llvm/lib/Target/PowerPC/PPCScheduleG3.td
diff -u llvm/lib/Target/PowerPC/PPCScheduleG3.td:1.3 llvm/lib/Target/PowerPC/PPCScheduleG3.td:1.4
--- llvm/lib/Target/PowerPC/PPCScheduleG3.td:1.3 Wed Oct 19 08:34:52 2005
+++ llvm/lib/Target/PowerPC/PPCScheduleG3.td Wed Oct 19 14:51:16 2005
@@ -31,9 +31,9 @@
InstrItinData<LdStDCBA , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
- InstrItinData<LdStDCBT , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStGeneral , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStICBI , [InstrStage<3, [SLU]>]>,
- InstrItinData<LdStLBZUX , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStUX , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>,
@@ -59,5 +59,5 @@
InstrItinData<FPDivD , [InstrStage<31, [FPU1]>]>,
InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>,
InstrItinData<FPFused , [InstrStage<2, [FPU1]>]>,
- InstrItinData<FPRes , [InstrStage<10, [FPU1]>]>,
+ InstrItinData<FPRes , [InstrStage<10, [FPU1]>]>
]>;
Index: llvm/lib/Target/PowerPC/PPCScheduleG4.td
diff -u llvm/lib/Target/PowerPC/PPCScheduleG4.td:1.3 llvm/lib/Target/PowerPC/PPCScheduleG4.td:1.4
--- llvm/lib/Target/PowerPC/PPCScheduleG4.td:1.3 Wed Oct 19 08:34:52 2005
+++ llvm/lib/Target/PowerPC/PPCScheduleG4.td Wed Oct 19 14:51:16 2005
@@ -30,15 +30,15 @@
InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>,
InstrItinData<LdStDCBF , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStDCBI , [InstrStage<2, [SLU]>]>,
- InstrItinData<LdStDCBT , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStGeneral , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStDSS , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStICBI , [InstrStage<2, [SLU]>]>,
- InstrItinData<LdStLBZUX , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStUX , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>,
- InstrItinData<LdStLVEBX , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStLVecX , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTVEBX , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStSTWCX , [InstrStage<5, [SLU]>]>,
Index: llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td
diff -u llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td:1.3 llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td:1.4
--- llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td:1.3 Wed Oct 19 08:34:52 2005
+++ llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td Wed Oct 19 14:51:16 2005
@@ -30,15 +30,15 @@
InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>,
InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
- InstrItinData<LdStDCBT , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStGeneral , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>,
- InstrItinData<LdStLBZUX , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStUX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>,
InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>,
InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>,
- InstrItinData<LdStLVEBX , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLWA , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
Index: llvm/lib/Target/PowerPC/PPCScheduleG5.td
diff -u llvm/lib/Target/PowerPC/PPCScheduleG5.td:1.3 llvm/lib/Target/PowerPC/PPCScheduleG5.td:1.4
--- llvm/lib/Target/PowerPC/PPCScheduleG5.td:1.3 Wed Oct 19 08:34:52 2005
+++ llvm/lib/Target/PowerPC/PPCScheduleG5.td Wed Oct 19 14:51:16 2005
@@ -34,17 +34,17 @@
InstrItinData<BrMCR , [InstrStage<2, [BPU]>]>,
InstrItinData<BrMCRX , [InstrStage<3, [BPU]>]>,
InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
- InstrItinData<LdStDCBT , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStGeneral , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDSS , [InstrStage<10, [SLU]>]>,
InstrItinData<LdStICBI , [InstrStage<40, [SLU]>]>,
- InstrItinData<LdStLBZUX , [InstrStage<4, [SLU]>]>,
+ InstrItinData<LdStUX , [InstrStage<4, [SLU]>]>,
InstrItinData<LdStLD , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLDARX , [InstrStage<11, [SLU]>]>,
InstrItinData<LdStLFD , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLFDU , [InstrStage<5, [SLU]>]>,
InstrItinData<LdStLHA , [InstrStage<5, [SLU]>]>,
InstrItinData<LdStLMW , [InstrStage<64, [SLU]>]>,
- InstrItinData<LdStLVEBX , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLWA , [InstrStage<5, [SLU]>]>,
InstrItinData<LdStLWARX , [InstrStage<11, [SLU]>]>,
InstrItinData<LdStSLBIA , [InstrStage<40, [SLU]>]>, // needs work
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