[llvm-commits] CVS: llvm/lib/Target/Target.td

[Jim Laskey]

Changes in directory llvm/lib/Target:

Target.td updated: 1.53 -> 1.54
---
Log message:

Added InstrSchedClass to each of the PowerPC Instructions.

Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.



---
Diffs of the changes:  (+8 -5)

 Target.td |   13 ++++++++-----
 1 files changed, 8 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.53 llvm/lib/Target/Target.td:1.54
--- llvm/lib/Target/Target.td:1.53	Wed Oct 19 08:34:52 2005
+++ llvm/lib/Target/Target.td	Wed Oct 19 14:51:16 2005
@@ -113,6 +113,12 @@
 
 
 //===----------------------------------------------------------------------===//
+// Pull in the common support for scheduling
+//
+include "../TargetSchedule.td"
+
+
+//===----------------------------------------------------------------------===//
 // Instruction set description - These classes correspond to the C++ classes in
 // the Target/TargetInstrInfo.h file.
 //
@@ -147,6 +153,8 @@
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
   bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
+  
+  InstrItinClass Itinerary; // Execution steps used for scheduling. 
 }
 
 
@@ -242,11 +250,6 @@
 }
 
 //===----------------------------------------------------------------------===//
-// Pull in the common support for scheduling
-//
-include "../TargetSchedule.td"
-
-//===----------------------------------------------------------------------===//
 // SubtargetFeature - A characteristic of the chip set.
 //
 class SubtargetFeature<string n, string d> {