[llvm-commits] CVS: llvm/lib/Target/Target.td TargetSchedule.td

[Jim Laskey]

Changes in directory llvm/lib/Target:

Target.td updated: 1.52 -> 1.53
TargetSchedule.td updated: 1.1 -> 1.2
---
Log message:

Push processor descriptions to the top of target and add command line info.


---
Diffs of the changes:  (+40 -9)

 Target.td         |   39 +++++++++++++++++++++++++++++++++++++++
 TargetSchedule.td |   10 +---------
 2 files changed, 40 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.52 llvm/lib/Target/Target.td:1.53
--- llvm/lib/Target/Target.td:1.52	Mon Oct 10 01:00:30 2005
+++ llvm/lib/Target/Target.td	Wed Oct 19 08:34:52 2005
@@ -242,6 +242,45 @@
 }
 
 //===----------------------------------------------------------------------===//
+// Pull in the common support for scheduling
+//
+include "../TargetSchedule.td"
+
+//===----------------------------------------------------------------------===//
+// SubtargetFeature - A characteristic of the chip set.
+//
+class SubtargetFeature<string n, string d> {
+  // Name - Feature name.  Used by command line (-mattr=) to determine the
+  // appropriate target chip.
+  //
+  string Name = n;
+  
+  // Desc - Feature description.  Used by command line (-mattr=) to display help
+  // information.
+  //
+  string Desc = d;
+}
+
+//===----------------------------------------------------------------------===//
+// Processor chip sets - These values represent each of the chip sets supported
+// by the scheduler.  Each Processor definition requires corresponding
+// instruction itineraries.
+//
+class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
+  // Name - Chip set name.  Used by command line (-mcpu=) to determine the
+  // appropriate target chip.
+  //
+  string Name = n;
+  
+  // ProcItin - The scheduling information for the target processor.
+  //
+  ProcessorItineraries ProcItin = pi;
+  
+  // Features - list of 
+  list<SubtargetFeature> Features;
+}
+
+//===----------------------------------------------------------------------===//
 // Pull in the common support for DAG isel generation
 //
 include "../TargetSelectionDAG.td"


Index: llvm/lib/Target/TargetSchedule.td
diff -u llvm/lib/Target/TargetSchedule.td:1.1 llvm/lib/Target/TargetSchedule.td:1.2
--- llvm/lib/Target/TargetSchedule.td:1.1	Tue Oct 18 11:23:40 2005
+++ llvm/lib/Target/TargetSchedule.td	Wed Oct 19 08:34:52 2005
@@ -13,13 +13,6 @@
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
-// Processor chip sets - These values represent each of the chip sets supported
-// by the scheduler.  Each Processor definition requires corresponding
-// instruction itineraries.
-//
-class Processor;
-
-//===----------------------------------------------------------------------===//
 // Processor functional unit - These values represent the function units
 // available across all chip sets for the target.  Eg., IntUnit, FPUnit, ...
 // These may be independent values for each chip set or may be shared across
@@ -68,7 +61,6 @@
 // Processor itineraries - These values represent the set of all itinerary
 // classes for a given chip set.
 //
-class ProcessorItineraries<Processor proc, list<InstrItinData> iid> {
-  Processor Proc = proc;
+class ProcessorItineraries<list<InstrItinData> iid> {
   list<InstrItinData> IID = iid;
 }