[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCInstrInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelDAGToDAG.cpp updated: 1.111 -> 1.112
PPCInstrInfo.td updated: 1.126 -> 1.127
---
Log message:

Convert these cases to patterns


---
Diffs of the changes:  (+11 -37)

 PPCISelDAGToDAG.cpp |   28 ----------------------------
 PPCInstrInfo.td     |   20 +++++++++++---------
 2 files changed, 11 insertions(+), 37 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.111 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.112
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.111	Tue Oct 18 20:12:32 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp	Tue Oct 18 20:38:02 2005
@@ -1211,34 +1211,6 @@
       
     // Other cases are autogenerated.
     break;
-  case ISD::TRUNCATE: {
-    assert(N->getValueType(0) == MVT::i32 && 
-           N->getOperand(0).getValueType() == MVT::i64 &&
-           "TRUNCATE only supported for i64 -> i32");
-    SDOperand Op0 = Select(N->getOperand(0));
-    CurDAG->SelectNodeTo(N, PPC::OR8To4, MVT::i32, Op0, Op0);
-    break;
-  }
-  case ISD::ANY_EXTEND:
-    switch(N->getValueType(0)) {
-    default: assert(0 && "Unhandled type in ANY_EXTEND");
-    case MVT::i64: {
-      SDOperand Op0 = Select(N->getOperand(0));
-      CurDAG->SelectNodeTo(N, PPC::OR4To8, MVT::i64, Op0, Op0);
-      break;
-    }
-    }
-    return SDOperand(N, 0);
-  case ISD::ZERO_EXTEND: {
-    assert(N->getValueType(0) == MVT::i64 && 
-           N->getOperand(0).getValueType() == MVT::i32 &&
-           "ZERO_EXTEND only supported for i32 -> i64");
-    SDOperand Op0 = Select(N->getOperand(0));
-    Op0 = CurDAG->getTargetNode(PPC::OR4To8, MVT::i64, Op0, Op0);
-    CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Op0, getI32Imm(0),
-                         getI32Imm(32));
-    return SDOperand(N, 0);
-  }
   case ISD::SHL: {
     unsigned Imm, SH, MB, ME;
     if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.126 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.127
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.126	Tue Oct 18 20:12:32 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Tue Oct 18 20:38:02 2005
@@ -18,14 +18,8 @@
 //===----------------------------------------------------------------------===//
 // PowerPC specific transformation functions and pattern fragments.
 //
-def GET_ZERO : SDNodeXForm<imm, [{
-  // Transformation function: get the low 16 bits.
-  return getI32Imm(0);
-}]>;
-def GET_32 : SDNodeXForm<imm, [{
-  // Transformation function: get the low 16 bits.
-  return getI32Imm(32);
-}]>;
+def GET_ZERO : SDNodeXForm<add, [{return getI32Imm(0);}]>;  // HACK
+def GET_32 : SDNodeXForm<add, [{ return getI32Imm(32);}]>;  // HACK
 
 def LO16 : SDNodeXForm<imm, [{
   // Transformation function: get the low 16 bits.
@@ -716,7 +710,15 @@
 // XOR an arbitrary immediate.
 def : Pat<(xor GPRC:$in, imm:$imm),
           (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
-          
+
+def : Pat<(zext GPRC:$in),
+          (RLDICL (OR4To8 GPRC:$in, GPRC:$in), (GET_ZERO imm:$in),
+           (GET_32 imm:$in))>;
+def : Pat<(anyext GPRC:$in),
+          (OR4To8 GPRC:$in, GPRC:$in)>;
+def : Pat<(trunc G8RC:$in),
+          (OR8To4 G8RC:$in, G8RC:$in)>;
+
 // Same as above, but using a temporary. FIXME: implement temporaries :)
 /*
 def : Pattern<(xor GPRC:$in, imm:$imm),