[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
Chris Lattner
lattner at cs.uiuc.edu
Tue Oct 18 17:18:07 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.td updated: 1.19 -> 1.20
---
Log message:
apply some tblgen majik to simplify the X register definitions
---
Diffs of the changes: (+19 -19)
PPCRegisterInfo.td | 38 +++++++++++++++++++-------------------
1 files changed, 19 insertions(+), 19 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.19 llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.20
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.19 Tue Oct 18 19:05:37 2005
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td Tue Oct 18 19:17:55 2005
@@ -22,10 +22,10 @@
}
// GP8 - One of the 32 64-bit general-purpose registers
-class GP8<bits<5> num, string n, Register Alias> : PPCReg<n> {
- field bits<5> Num = num;
+class GP8<GPR Alias> : PPCReg<Alias.Name> {
+ field bits<5> Num = Alias.Num;
let Aliases = [Alias];
-}
+}
// SPR - One of the 32-bit special-purpose registers
class SPR<bits<5> num, string n> : PPCReg<n> {
@@ -61,22 +61,22 @@
def R30 : GPR<30, "r30">; def R31 : GPR<31, "r31">;
// 64-bit General-purpose registers
-def X0 : GP8< 0, "r0", R0>; def X1 : GP8< 1, "r1", R1>;
-def X2 : GP8< 2, "r2", R2>; def X3 : GP8< 3, "r3", R3>;
-def X4 : GP8< 4, "r4", R4>; def X5 : GP8< 5, "r5", R5>;
-def X6 : GP8< 6, "r6", R6>; def X7 : GP8< 7, "r7", R7>;
-def X8 : GP8< 8, "r8", R8>; def X9 : GP8< 9, "r9", R9>;
-def X10 : GP8<10, "r10", R10>; def X11 : GP8<11, "r11", R11>;
-def X12 : GP8<12, "r12", R12>; def X13 : GP8<13, "r13", R13>;
-def X14 : GP8<14, "r14", R14>; def X15 : GP8<15, "r15", R15>;
-def X16 : GP8<16, "r16", R16>; def X17 : GP8<17, "r17", R17>;
-def X18 : GP8<18, "r18", R18>; def X19 : GP8<19, "r19", R19>;
-def X20 : GP8<20, "r20", R20>; def X21 : GP8<21, "r21", R21>;
-def X22 : GP8<22, "r22", R22>; def X23 : GP8<23, "r23", R23>;
-def X24 : GP8<24, "r24", R24>; def X25 : GP8<25, "r25", R25>;
-def X26 : GP8<26, "r26", R26>; def X27 : GP8<27, "r27", R27>;
-def X28 : GP8<28, "r28", R28>; def X29 : GP8<29, "r29", R29>;
-def X30 : GP8<30, "r30", R30>; def X31 : GP8<31, "r31", R31>;
+def X0 : GP8< R0>; def X1 : GP8< R1>;
+def X2 : GP8< R2>; def X3 : GP8< R3>;
+def X4 : GP8< R4>; def X5 : GP8< R5>;
+def X6 : GP8< R6>; def X7 : GP8< R7>;
+def X8 : GP8< R8>; def X9 : GP8< R9>;
+def X10 : GP8<R10>; def X11 : GP8<R11>;
+def X12 : GP8<R12>; def X13 : GP8<R13>;
+def X14 : GP8<R14>; def X15 : GP8<R15>;
+def X16 : GP8<R16>; def X17 : GP8<R17>;
+def X18 : GP8<R18>; def X19 : GP8<R19>;
+def X20 : GP8<R20>; def X21 : GP8<R21>;
+def X22 : GP8<R22>; def X23 : GP8<R23>;
+def X24 : GP8<R24>; def X25 : GP8<R25>;
+def X26 : GP8<R26>; def X27 : GP8<R27>;
+def X28 : GP8<R28>; def X29 : GP8<R29>;
+def X30 : GP8<R30>; def X31 : GP8<R31>;
// Floating-point registers
def F0 : FPR< 0, "f0">; def F1 : FPR< 1, "f1">;
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