[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

[Nate Begeman]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.90 -> 1.91
---
Log message:

Add the ability to lower return instructions to TargetLowering.  This
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).


---
Diffs of the changes:  (+7 -2)

 SelectionDAGISel.cpp |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.90 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.91
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.90	Tue Oct 18 17:14:06 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Tue Oct 18 18:23:37 2005
@@ -450,8 +450,8 @@
   case MVT::f64:
     break; // No extension needed!
   }
-
-  DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot(), Op1));
+  // Allow targets to lower this further to meet ABI requirements
+  DAG.setRoot(TLI.LowerReturnTo(getRoot(), Op1, DAG));
 }
 
 void SelectionDAGLowering::visitBr(BranchInst &I) {
@@ -898,6 +898,11 @@
   return 0;  
 }
 
+SDOperand TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
+                                        SelectionDAG &DAG) {
+  return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
+}
+
 SDOperand TargetLowering::LowerVAStart(SDOperand Chain,
                                        SDOperand VAListP, Value *VAListV,
                                        SelectionDAG &DAG) {