[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCSubtarget.cpp PPCSubtarget.h

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.32 -> 1.33
PPCSubtarget.cpp updated: 1.9 -> 1.10
PPCSubtarget.h updated: 1.7 -> 1.8
---
Log message:

Do the right thing and enable 64 bit regs under the control of a subtarget
option.  Currently the only way to enable this is to specify the
64bitregs mattr flag.  It is never enabled by default on any config yet.


---
Diffs of the changes:  (+10 -8)

 PPCISelLowering.cpp |   13 +++++--------
 PPCSubtarget.cpp    |    3 +++
 PPCSubtarget.h      |    2 ++
 3 files changed, 10 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.32 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.33
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.32	Mon Oct 17 19:28:58 2005
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Mon Oct 17 19:56:42 2005
@@ -94,19 +94,16 @@
   setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
   
   if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
-    // 64 bit PowerPC implementations can support i64 types directly
-    // FIXME: enable this once it works.
-    //addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
     // They also have instructions for converting between i64 and fp.
     setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
     setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
+  }
+
+  if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
+    // 64 bit PowerPC implementations can support i64 types directly
+    addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
     // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
     setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
-    // 32 bit PowerPC wants to expand i64 shifts itself.
-    // FIXME: remove these once we natively handle i64 shifts.
-    setOperationAction(ISD::SHL, MVT::i64, Custom);
-    setOperationAction(ISD::SRL, MVT::i64, Custom);
-    setOperationAction(ISD::SRA, MVT::i64, Custom);
   } else {
     // 32 bit PowerPC wants to expand i64 shifts itself.
     setOperationAction(ISD::SHL, MVT::i64, Custom);


Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
diff -u llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.9 llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.10
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.9	Fri Oct 14 18:51:18 2005
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp	Mon Oct 17 19:56:42 2005
@@ -36,6 +36,7 @@
   PowerPCFeatureAltivec = 1 << 1,
   PowerPCFeatureFSqrt   = 1 << 2,
   PowerPCFeatureGPUL    = 1 << 3,
+  PowerPCFeature64BRegs = 1 << 4
 };
 
 /// Sorted (by key) array of values for CPU subtype.
@@ -73,6 +74,7 @@
 /// Sorted (by key) array of values for CPU features.
 static SubtargetFeatureKV PowerPCFeatureKV[] = {
   { "64bit"  , "Should 64 bit instructions be used"  , PowerPCFeature64Bit   },
+  { "64bitregs", "Should 64 bit registers be used"   , PowerPCFeature64BRegs },
   { "altivec", "Should Altivec instructions be used" , PowerPCFeatureAltivec },
   { "fsqrt"  , "Should the fsqrt instruction be used", PowerPCFeatureFSqrt   },
   { "gpul"   , "Should GPUL instructions be used"    , PowerPCFeatureGPUL    }
@@ -134,6 +136,7 @@
   IsGigaProcessor = (Bits & PowerPCFeatureGPUL ) != 0;
   Is64Bit         = (Bits & PowerPCFeature64Bit) != 0;
   HasFSQRT        = (Bits & PowerPCFeatureFSqrt) != 0;
+  Has64BitRegs    = (Bits & PowerPCFeature64BRegs) != 0;
 
   // Set the boolean corresponding to the current target triple, or the default
   // if one cannot be determined, to true.


Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
diff -u llvm/lib/Target/PowerPC/PPCSubtarget.h:1.7 llvm/lib/Target/PowerPC/PPCSubtarget.h:1.8
--- llvm/lib/Target/PowerPC/PPCSubtarget.h:1.7	Sun Oct 16 00:39:50 2005
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h	Mon Oct 17 19:56:42 2005
@@ -30,6 +30,7 @@
   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
   bool IsGigaProcessor;
   bool Is64Bit;
+  bool Has64BitRegs;
   bool HasFSQRT;
   bool IsAIX;
   bool IsDarwin;
@@ -49,6 +50,7 @@
   bool isAIX() const { return IsAIX; }
   bool isDarwin() const { return IsDarwin; }
   bool is64Bit() const { return Is64Bit; }
+  bool has64BitRegs() const { return Has64BitRegs; }
   bool isGigaProcessor() const { return IsGigaProcessor; }
 };
 } // End llvm namespace