[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.42 -> 1.43
---
Log message:

Fix this logic.


---
Diffs of the changes:  (+1 -1)

 DAGCombiner.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.42 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.43
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.42	Sat Oct 15 17:18:08 2005
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Sat Oct 15 17:35:40 2005
@@ -808,7 +808,7 @@
     if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
       // If the RHS of the AND has zeros where the sign bits of the SRA will
       // land, turn the SRA into an SRL.
-      if (MaskedValueIsZero(N1, (~0ULL << N01C->getValue()) &
+      if (MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) &
                             (~0ULL>>(64-OpSizeInBits)), TLI)) {
         WorkList.push_back(N);
         CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),