[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32.td PowerPC.td PowerPCRegisterInfo.td PPC32RegisterInfo.td

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPC32.td updated: 1.4 -> 1.5
PowerPC.td updated: 1.13 -> 1.14
PowerPCRegisterInfo.td updated: 1.16 -> 1.17
PPC32RegisterInfo.td (r1.8) removed
---
Log message:

Remove an unnecsesary file.  PPC32 and PPC64 share architected registers.
We will decide with subtarget support whether we ever use an i64 register
class.


---
Diffs of the changes:  (+38 -2)

 PPC32.td               |    2 +-
 PowerPC.td             |    2 +-
 PowerPCRegisterInfo.td |   36 ++++++++++++++++++++++++++++++++++++
 3 files changed, 38 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32.td
diff -u llvm/lib/Target/PowerPC/PPC32.td:1.4 llvm/lib/Target/PowerPC/PPC32.td:1.5
--- llvm/lib/Target/PowerPC/PPC32.td:1.4	Thu Dec 16 10:31:57 2004
+++ llvm/lib/Target/PowerPC/PPC32.td	Fri Oct 14 13:58:46 2005
@@ -18,7 +18,7 @@
 // Register File Description
 //===----------------------------------------------------------------------===//
 
-include "PPC32RegisterInfo.td"
+include "PowerPCRegisterInfo.td"
 include "PowerPCInstrInfo.td"
 
 def PPC32 : Target {


Index: llvm/lib/Target/PowerPC/PowerPC.td
diff -u llvm/lib/Target/PowerPC/PowerPC.td:1.13 llvm/lib/Target/PowerPC/PowerPC.td:1.14
--- llvm/lib/Target/PowerPC/PowerPC.td:1.13	Thu Sep 29 19:05:05 2005
+++ llvm/lib/Target/PowerPC/PowerPC.td	Fri Oct 14 13:58:46 2005
@@ -18,7 +18,7 @@
 // Register File Description
 //===----------------------------------------------------------------------===//
 
-include "PPC32RegisterInfo.td"
+include "PowerPCRegisterInfo.td"
 include "PowerPCInstrInfo.td"
 
 def PowerPC : Target {


Index: llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td:1.16 llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td:1.17
--- llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td:1.16	Mon Aug 22 17:32:13 2005
+++ llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td	Fri Oct 14 13:58:46 2005
@@ -84,3 +84,39 @@
 // Count register
 def CTR : SPR<3, "ctr">;
 
+/// Register classes
+// Allocate volatiles first
+// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
+def GPRC : RegisterClass<"PPC32", i32, 32,
+     [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
+      R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
+      R16, R15, R14, R13, R31, R0, R1, LR]>
+{
+  let MethodProtos = [{
+    iterator allocation_order_begin(MachineFunction &MF) const;
+    iterator allocation_order_end(MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    GPRCClass::iterator
+    GPRCClass::allocation_order_begin(MachineFunction &MF) const {
+      return begin() + ((TargetAIX == PPCTarget) ? 1 : 0);
+    }
+    GPRCClass::iterator
+    GPRCClass::allocation_order_end(MachineFunction &MF) const {
+      if (hasFP(MF))
+        return end()-4;
+      else
+        return end()-3;
+    }
+  }];
+}
+
+def F8RC : RegisterClass<"PPC32", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
+  F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
+  F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
+def F4RC : RegisterClass<"PPC32", f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7,
+  F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
+  F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
+
+
+def CRRC : RegisterClass<"PPC32", i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>;