[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetSelectionDAG.td updated: 1.1 -> 1.2
---
Log message:

add a new SDTCisOpSmallerThanOp type constraint, and implement fround/fextend in terms of it


---
Diffs of the changes:  (+13 -0)

 TargetSelectionDAG.td |   13 +++++++++++++
 1 files changed, 13 insertions(+)


Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.1 llvm/lib/Target/TargetSelectionDAG.td:1.2
--- llvm/lib/Target/TargetSelectionDAG.td:1.1	Mon Oct 10 01:00:30 2005
+++ llvm/lib/Target/TargetSelectionDAG.td	Thu Oct 13 23:55:10 2005
@@ -45,6 +45,10 @@
   int OtherOperandNum = OtherOp;
 }
 
+class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
+  int BigOperandNum = BigOp;
+}
+
 //===----------------------------------------------------------------------===//
 // Selection DAG Type Profile definitions.
 //
@@ -77,6 +81,12 @@
 def SDTFPUnaryOp  : SDTypeProfile<1, 1, [   // fneg, fsqrt, etc
   SDTCisSameAs<0, 1>, SDTCisFP<0>
 ]>;
+def SDTFPRoundOp  : SDTypeProfile<1, 1, [   // fround
+  SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
+]>;
+def SDTFPExtendOp  : SDTypeProfile<1, 1, [   // fextend
+  SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
+]>;
 def SDTExtInreg : SDTypeProfile<1, 2, [   // sext_inreg
   SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
   SDTCisVTSmallerThanOp<2, 1>
@@ -136,6 +146,9 @@
 def fneg       : SDNode<"ISD::FNEG"       , SDTFPUnaryOp>;
 def fsqrt      : SDNode<"ISD::FSQRT"      , SDTFPUnaryOp>;
 
+def fround     : SDNode<"ISD::FP_ROUND"   , SDTFPRoundOp>;
+def fextend    : SDNode<"ISD::FP_EXTEND"  , SDTFPExtendOp>;
+
 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
 def ctlz       : SDNode<"ISD::CTLZ"      , SDTIntUnaryOp>;