[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Chris Lattner
lattner at cs.uiuc.edu
Sun Oct 9 15:12:48 PDT 2005
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.22 -> 1.23
---
Log message:
(X & Y) & C == 0 if either X&C or Y&C are zero
---
Diffs of the changes: (+6 -1)
DAGCombiner.cpp | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.22 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.23
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.22 Fri Oct 7 19:29:44 2005
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Oct 9 17:12:36 2005
@@ -176,10 +176,15 @@
SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
case ISD::AND:
+ // If either of the operands has zero bits, the result will too.
+ if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
+ MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
+ return true;
+
// (X & C1) & C2 == 0 iff C1 & C2 == 0.
if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
- // FALL THROUGH
+ return false;
case ISD::OR:
case ISD::XOR:
return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
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