[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.202 -> 1.203
---
Log message:

(X & Y) & C == 0 if either X&C or Y&C are zero


---
Diffs of the changes:  (+6 -2)

 SelectionDAG.cpp |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.202 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.203
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.202	Fri Oct  7 10:31:26 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Sun Oct  9 17:09:50 2005
@@ -608,11 +608,15 @@
     SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
     return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
   case ISD::AND:
+    // If either of the operands has zero bits, the result will too.
+    if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
+        MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
+      return true;
+
     // (X & C1) & C2 == 0   iff   C1 & C2 == 0.
     if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
       return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
-    
-    // FALL THROUGH
+    return false;
   case ISD::OR:
   case ISD::XOR:
     return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&