[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.98 -> 1.99
---
Log message:

Disable formation of rlwinm instructions from SRA bases.  This fixes 
the 177.mesa failure from last night, and fixes the
CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll regression test I added.
If this code cannot be fixed, it should be removed for good, but I'll leave
it to Nate to decide its fate.


---
Diffs of the changes:  (+2 -2)

 PPC32ISelDAGToDAG.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.98 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.99
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.98	Fri Oct  7 17:10:27 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Sun Oct  9 00:36:17 2005
@@ -217,7 +217,7 @@
   return false;
 }
 
-// isRotateAndMask - Returns true if Mask and Shift can be folded in to a rotate
+// isRotateAndMask - Returns true if Mask and Shift can be folded into a rotate
 // and mask opcode and mask operation.
 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
                             unsigned &SH, unsigned &MB, unsigned &ME) {
@@ -1278,7 +1278,7 @@
   }
   case ISD::SRA: {
     unsigned Imm, SH, MB, ME;
-    if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
+    if (0 &&isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
         isRotateAndMask(N, Imm, true, SH, MB, ME))
       CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, 
                            Select(N->getOperand(0).getOperand(0)),